文件列表:

CAST_jpeg_d-xact\JPEG_D\doc\jpeg-d-des-2v03ns00-103.pdf (213156, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\IPinfo.txt (1590, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\add_4_4_5.v (2694, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\add_5_5_5.v (3172, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\add_6_4_6.v (2868, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\add_8_16_16.v (2609, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\add_8_16_8.v (2653, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\add_8_8_8.v (2564, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\amplitude_gen.v (6045, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\barrel_shifter_32to16.v (3691, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\barrel_shifter_64to32.v (4639, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\base_reg_file.v (4834, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\codelength_reg_file.v (5676, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\comparators.v (4728, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\del_lines.v (5871, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\din_select.v (5267, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\dreg_1.v (2848, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\dreg_1_en.v (3237, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\dreg_n_en.v (3148, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\eob_out.v (3018, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\huffman_d.v (21433, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\huffman_d_int_memories.v (5980, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\huffman_d_int_tables_both.v (8594, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\huffman_d_int_tables_single.v (7362, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\huffman_d_no_mem.v (21607, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\huffman_d_tables.v (8639, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\inc_4.v (2459, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\left_shift_1_16.v (2544, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\length_select.v (5267, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\min_code_reg_file.v (6803, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\mux_2_1_n.v (2718, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\offset_gen.v (2868, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\program.v (15836, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\reg_n.v (3407, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\sub_8_16_8.v (2783, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\symbol_memory_both.v (2823, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\huffman_d\tables_if.v (8684, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\idct\convert_io.v (5332, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\idct\cos_constants.v (10694, 2008-04-14)
CAST_jpeg_d-xact\JPEG_D\openip\hdl\verilog\idct\cos_constants_package.v (2790, 2008-04-14)
... ...

----------------------------------------------------------------------------- -- Copyright (c) 2008 Alma Technologies S.A. ----------------------------------------------------------------------------- Quick synthesis guide : ----------------------- 1. In Synplify's UI open ./openip/synplify/jpeg_d.prj project file 2. Choose an implementation (implementations are named after the FPGA family) 3. Click run Add RTL sources in your own project : ------------------------------------_ 1. Edit the ./openip/synplify/sample_script/read_files.tcl, so that you set the RTL sources relative path (if necessary). 2. In Synplify's UI select "Run->Run tcl script..." tab 3. Select the ./openip/synplify/sample_script/read_files.tcl, and click the "Open" tab Top-level module : ------------------ The RTL of the top-level module (jpeg_d.v) is provided unencrypted under the directory ./openip/hdl/verilog/jpeg_d.

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