div(FLP)
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：18KB
下载次数：45
上传日期：2009-03-17 18:31:52
上 传 者：
sakiuke
说明： 是Nios II處理器下客製化指令的一個32位元浮點數除法器，可將兩IEEE 754格式的值進行相除
(Nios II processors are customized instruction under a 32-bit floating-point divider can be two format IEEE 754 value division)
文件列表:
div(FLP)\conv.vhd (2239, 2004-07-12)
div(FLP)\csa_1bit.vhd (1231, 2004-07-12)
div(FLP)\csa_1weight_odd.vhd (2475, 2004-07-12)
div(FLP)\csa_2weight.vhd (3882, 2004-07-12)
div(FLP)\cube24.vhd (690, 2004-07-12)
div(FLP)\fa_1bit.vhd (632, 2004-07-12)
div(FLP)\fpdivider24.vhd (4494, 2004-07-12)
div(FLP)\fpdivider24_v1.vhd (4640, 2004-07-12)
div(FLP)\fpdiv_32.vhd (4760, 2008-01-30)
div(FLP)\index.vhd (638, 2004-07-12)
div(FLP)\msub24_1bx_shell.vhd (3565, 2004-07-12)
div(FLP)\mult_ax.vhd (860, 2004-07-12)
div(FLP)\mult_final28.vhd (846, 2004-07-12)
div(FLP)\mult_sub24_1bx.vhd (14952, 2004-07-12)
div(FLP)\rca_20bit.vhd (1497, 2004-07-12)
div(FLP)\square24.vhd (656, 2004-07-12)
div(FLP)\sum28.vhd (1115, 2004-07-12)
div(FLP)\sum28_shell.vhd (2670, 2004-07-12)
div(FLP)\table.vhd (7836, 2004-07-12)
div(FLP)\table_shell.vhd (2191, 2004-07-12)
div(FLP)\transcript (449, 2008-01-30)
div(FLP)\truncate.vhd (964, 2004-07-12)
div(FLP)\vish_stacktrace.vstf (366, 2008-01-30)
div(FLP)\words.vhd (629, 2004-07-12)
div(FLP) (0, 2009-02-23)
近期下载者：
相关文件：
收藏者：