FIFO_8_8
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:5KB
下载次数:37
上传日期:2009-03-21 23:20:18
上 传 者:
plyx2003
说明: FIFO先进先出队列,一种缓存、或一种管道、设备、接口(Verilog HDL程序,内附说明)
(FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note))
文件列表:
FIFO_8_8\cmp_state.ini (1, 2006-08-09)
FIFO_8_8\db\FIFO_8_8.db_info (136, 2006-08-09)
FIFO_8_8\db\FIFO_8_8.eco.cdb (142, 2006-08-09)
FIFO_8_8\db\FIFO_8_8.sld_design_entry.sci (134, 2006-08-09)
FIFO_8_8\db (0, 2009-03-21)
FIFO_8_8\FIFO_8_8.qpf (1561, 2006-08-09)
FIFO_8_8\FIFO_8_8.qsf (2394, 2006-08-09)
FIFO_8_8\FIFO_8_8.qws (768, 2006-08-09)
FIFO_8_8\FIFO_8_8.v (1439, 2006-08-09)
FIFO_8_8 (0, 2009-03-21)
说明.txt (1472, 2009-03-21)
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