文件列表:

FIFO_EMIF\.lso (6, 2008-11-06)
FIFO_EMIF\chi_in.cdc (5372, 2008-10-30)
FIFO_EMIF\clkdcm.v (3541, 2008-11-06)
FIFO_EMIF\clkdcm.xaw (3407, 2008-10-30)
FIFO_EMIF\clkdcm_arwz.ucf (842, 2008-11-06)
FIFO_EMIF\datafifo.asy (878, 2008-11-06)
FIFO_EMIF\datafifo.ngc (77367, 2008-11-06)
FIFO_EMIF\datafifo.sym (1487, 2008-11-06)
FIFO_EMIF\datafifo.v (5267, 2008-11-06)
FIFO_EMIF\datafifo.veo (3102, 2008-11-06)
FIFO_EMIF\datafifo.vhd (5476, 2008-11-06)
FIFO_EMIF\datafifo.vho (3674, 2008-11-06)
FIFO_EMIF\datafifo.xco (2238, 2008-06-11)
FIFO_EMIF\datafifo_fifo_generator_v3_3_xst_1.lso (63, 2008-11-06)
FIFO_EMIF\datafifo_fifo_generator_v3_3_xst_1_vhdl.prj (18073, 2008-11-06)
FIFO_EMIF\datafifo_flist.txt (233, 2008-11-06)
FIFO_EMIF\datafifo_xmdf.tcl (3212, 2008-11-06)
FIFO_EMIF\device_usage_statistics.html (40487, 2008-11-06)
FIFO_EMIF\emif.ucf (2864, 2008-11-06)
FIFO_EMIF\fifo2dsp.bgn (6658, 2008-11-06)
FIFO_EMIF\fifo2dsp.bit (2843228, 2008-11-06)
FIFO_EMIF\FIFO2DSP.bld (4316, 2008-11-06)
FIFO_EMIF\FIFO2DSP.cmd_log (6270, 2008-11-06)
FIFO_EMIF\fifo2dsp.drc (38, 2008-11-06)
FIFO_EMIF\FIFO2DSP.lso (6, 2008-11-06)
FIFO_EMIF\FIFO2DSP.mcs (7997126, 2008-11-06)
FIFO_EMIF\FIFO2DSP.ncd (95990, 2008-11-06)
FIFO_EMIF\FIFO2DSP.ngc (95839, 2008-11-06)
FIFO_EMIF\FIFO2DSP.ngd (229232, 2008-11-06)
FIFO_EMIF\FIFO2DSP.ngr (60112, 2008-11-06)
FIFO_EMIF\FIFO2DSP.pad (44448, 2008-11-06)
FIFO_EMIF\FIFO2DSP.par (7967, 2008-11-06)
FIFO_EMIF\FIFO2DSP.pcf (2242, 2008-11-06)
FIFO_EMIF\FIFO2DSP.prj (113, 2008-11-06)
FIFO_EMIF\FIFO2DSP.prm (613, 2008-11-06)
FIFO_EMIF\FIFO2DSP.sig (219, 2008-11-06)
FIFO_EMIF\FIFO2DSP.stx (0, 2008-11-06)
FIFO_EMIF\FIFO2DSP.syr (33577, 2008-11-06)
FIFO_EMIF\fifo2dsp.twr (5946, 2008-11-06)
... ...

The following files were generated for 'datafifo' in directory E:\FPGA\FPGA_Prog\emif2DSP\FPGA_EMIF_2_DSP\FIFO_EMIF: datafifo.asy: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. datafifo.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA. datafifo.sym: Please see the core data sheet. datafifo.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. datafifo.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design. datafifo.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. datafifo.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. datafifo.xco: CORE Generator input file containing the parameters used to regenerate a core. datafifo_fifo_generator_v3_3_xst_1_vhdl.prj: Please see the core data sheet. datafifo_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. datafifo_readme.txt: Text file indicating the files generated and how they are used. datafifo_xmdf.tcl: Please see the core data sheet. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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