文件列表:

freqm\control.asf (3384, 2001-02-07)
freqm\freqm.ise (222930, 2007-02-25)
freqm\cnt_bcd.sym (1444, 2003-03-14)
freqm\control.sym (945, 2003-03-14)
freqm\hex2led.sym (567, 2003-03-14)
freqm\bcd_cnt.vhd (1569, 2001-02-07)
freqm\control.vhd (1128, 2001-02-07)
freqm\freqm_tb.vhd (1737, 2001-06-16)
freqm\hex2led.vhd (833, 2001-02-07)
freqm\freqm.sch (6697, 2005-09-20)

-- Copyright(C) 2006 by Xilinx, Inc. All rights reserved. -- The files included in this design directory contain proprietary, confidential information of -- Xilinx, Inc., are distributed under license from Xilinx, Inc., and may be used, copied -- and/or disclosed only pursuant to the terms of a valid license agreement with Xilinx, Inc. -- This copyright notice must be retained as part of this text at all times. Description: The design is based upon the BCD-counter and the 7-segment LED display. The method of measurement is comparing the input signal frequency with the reference clock signal that is faster than the measured signal. The measurment is started by setting the START signal to '1'. Setting START back to '0' finishes the measurment and resets the meter. The design includes 3 blocks described as behavioral VHDL code that are synthesized and implemented in a Xilinx FPGA. Project FREQM is a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display. Design Type: ISE (chip 3S100E VQ100 -4) Inputs: FINPUT - measured frequency clock input FPATTERN - reference frequency clock input START - input logical signal starting the measurement, active HIGH RESET - asynchronous reset, active in HIGH. Outputs: four-positions 7-segment LED display LED_D[6:0] - the most significant decimal digit LED_C[6:0] - LED_B[6:0] - LED_A[6:0] - the least significant decimal digit FULL - counter overflow flag Simulation: Simulation requires the following libraries: Unisims Simprims Behavioural and RTL Simulation done using VHDL Testbench (freqm_tb.vhd). NOTE: If you are trying to run this example in a read-only location, the design hierachy will not display properly. Please copy the example project to a new location by using either Project Save As... from the File menu pulldown in ISE or some other method of your choice. Copy the example to a location where you have write permissions and the hiearchy will display properly. For support information and contacts please see: http://www.xilinx.com/support or http://www.xilinx.com/support/services/contact_info.htm

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：