文件列表:

LVDS_Serdes_list_FPGA1\bit_align_machine.bgn (6595, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.bld (947, 2008-08-19)
LVDS_Serdes_list_FPGA1\bit_align_machine.drc (131, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.ncd (33570, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.ngd (38316, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.pad (40128, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.par (5109, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.pcf (215, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.ptwx (16967, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.twr (3626, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.twx (21254, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.unroutes (156, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.ut (595, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.v (15127, 2006-08-07)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.vhd (23025, 2008-08-21)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.vhd.bak (23020, 2008-08-21)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE.xpi (46, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_guide.ncd (33570, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_map.map (3539, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_map.mrp (10029, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_map.ncd (17722, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_map.ngm (71173, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_map.xrpt (20871, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_ngdbuild.xrpt (971, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_pad.csv (40161, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_pad.txt (230276, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_par.xrpt (2500, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_prev_built.ngd (38316, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_summary.html (3186, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_summary.xml (408, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_usage.xml (16522, 2008-08-19)
LVDS_Serdes_list_FPGA1\BIT_ALIGN_MACHINE_xst.xrpt (4909, 2008-08-19)
LVDS_Serdes_list_FPGA1\bypass_bram.v (28609, 2008-08-05)
LVDS_Serdes_list_FPGA1\count_to_128.vhd (3163, 2006-08-15)
LVDS_Serdes_list_FPGA1\count_to_16x.vhd (2871, 2008-08-22)
LVDS_Serdes_list_FPGA1\COUNT_TO_64.vhd (3371, 2008-08-21)
LVDS_Serdes_list_FPGA1\CS.cdc (24349, 2008-12-03)
LVDS_Serdes_list_FPGA1\DDR_6TO1_16CHAN_RT_RX.bld (2089, 2008-08-21)
LVDS_Serdes_list_FPGA1\DDR_6TO1_16CHAN_RT_RX.ncd (403349, 2008-08-24)
LVDS_Serdes_list_FPGA1\DDR_6TO1_16CHAN_RT_RX.ngc (313569, 2008-08-24)
... ...

******************************************************************************* ** Copyright (c) 2006 Xilinx, Inc. ** All Rights Reserved ******************************************************************************* ** ____ ____ ** / /\/ / ** /___/ \ / Vendor: Xilinx ** \ \ \/ Version: 1.0 ** \ \ Filename: readme.txt ** / / Timestamp: 19 Sep 2006 ** /___/ /\ ** \ \ / \ ** \___\/\___\ ** ** ** Device: Virtex-5 ** Purpose: ** Readme file for contents of XAPP860.ZIP. These files are associated with ** the 16 Channel DDR LVDS Interface with Window Monitoring reference design outlined in XAPP860. ** 1. Implementation details: ** a. Synthesis/Place & Route software used to develop ** reference design. Specific software settings also mentioned here ** if appropriate. ** b. Platform used for hardware verification testing ** 2. Source code file descriptions ** 3. Build-related support file descriptions ** 4. General notes (if appropriate) ** ** Reference: ** XAPP860 ** Revision History: ** Rev 1.0 - First created, GBurton, 9/19/06 ** ** ******************************************************************************* ******************************************************************************* ** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are ** provided to you "as is". Xilinx and its licensors make and you ** receive no warranties or conditions, express, implied, ** statutory or otherwise, and Xilinx specifically disclaims any ** implied warranties of merchantability, non-infringement,or ** fitness for a particular purpose. Xilinx does not warrant that ** the functions contained in these designs will meet your ** requirements, or that the operation of these designs will be ** uninterrupted or error free, or that defects in the Designs ** will be corrected. Furthermore, Xilinx does not warrantor ** make any representations regarding use or the results of the ** use of the designs in terms of correctness, accuracy, ** reliability, or otherwise. ** ** LIMITATION OF LIABILITY. In no event will Xilinx or its ** licensors be liable for any loss of data, lost profits,cost ** or procurement of substitute goods or services, or for any ** special, incidental, consequential, or indirect damages ** arising from the use or operation of the designs or ** accompanying documentation, however caused and on any theory ** of liability. This limitation will apply even if Xilinx ** has been advised of the possibility of such damage. This ** limitation shall apply not-withstanding the failure of the ** essential purpose of any limited remedies herein. ** ** Copyright 2006 Xilinx, Inc. ** All rights reserved ** ******************************************************************************* ******************************************************************************* ** Implementation Details ******************************************************************************* HDL Language(s) - VHDL/Verilog Synthesis - XST, ISE 8.2i SP3 (I.34) Place/Route: - ISE 8.2i SP3 (I.34) Hardware Verification: Platform - ML550 Networking Interfaces Board Target Part - XC5VLX50T-FF1136 (all speed grades) Target Bus Width - 16-bit Target Bus Clock Speed - 1.0, 1.0, 1.2 Gb/s (-1, -2, -3) ******************************************************************************* ** File Descriptions and Design Hierarchy ******************************************************************************* The xapp860.zip archive includes the following subdirectories. The specific contents of each subdirectory below: \Verilog - Verilog design files \VHDL - VHDL Design files **************************************** ** HDL design files **************************************** Design Hierarchy for XAPP860 Reference Design NOTE: All file extentions are .vhd or .v 1. DDR_6TO1_16CHAN_RT_TX 2. DDR_6TO1_16CHAN_RT_RX a. RESOURCE_SHARING_CONTROL i. COUNT_TO_128 ii. COUNT_TO_16X b. BIT_ALIGN_MACHINE i. COUNT_TO_128 ii. SEVEN_BIT_REG_W_CE c. RT_WINDOW_MONITOR i. COUNT_TO_128 d. COUNT_TO_***

近期下载者：

相关文件：

评论：[我要评论] [举报此文件]

收藏者：