文件列表:

.\trunk (0, 2009-03-11)
.\trunk\bench (0, 2009-03-11)
.\trunk\bench\verilog (0, 2009-03-11)
.\trunk\bench\verilog\ac97_codec_sout.v (5795, 2009-03-11)
.\trunk\bench\verilog\tests.v (29231, 2009-03-11)
.\trunk\bench\verilog\ac97_codec_sin.v (5689, 2009-03-11)
.\trunk\bench\verilog\wb_model_defines.v (2819, 2009-03-11)
.\trunk\bench\verilog\ac97_codec_top.v (14634, 2009-03-11)
.\trunk\bench\verilog\wb_mast_model.v (9357, 2009-03-11)
.\trunk\bench\verilog\test_bench_top.v (21732, 2009-03-11)
.\trunk\rtl (0, 2009-03-11)
.\trunk\rtl\verilog (0, 2009-03-11)
.\trunk\rtl\verilog\ac97_soc.v (6106, 2009-03-11)
.\trunk\rtl\verilog\ac97_dma_if.v (6507, 2009-03-11)
.\trunk\rtl\verilog\ac97_prc.v (8447, 2009-03-11)
.\trunk\rtl\verilog\ac97_in_fifo.v (8829, 2009-03-11)
.\trunk\rtl\verilog\ac97_out_fifo.v (8486, 2009-03-11)
.\trunk\rtl\verilog\ac97_sout.v (5545, 2009-03-11)
.\trunk\rtl\verilog\ac97_sin.v (4430, 2009-03-11)
.\trunk\rtl\verilog\ac97_rst.v (3666, 2009-03-11)
.\trunk\rtl\verilog\ac97_int.v (4534, 2009-03-11)
.\trunk\rtl\verilog\ac97_defines.v (7124, 2009-03-11)
.\trunk\rtl\verilog\ac97_fifo_ctrl.v (4363, 2009-03-11)
.\trunk\rtl\verilog\ac97_cra.v (5744, 2009-03-11)
.\trunk\rtl\verilog\ac97_top.v (17479, 2009-03-11)
.\trunk\rtl\verilog\ac97_rf.v (9102, 2009-03-11)
.\trunk\rtl\verilog\ac97_wb_if.v (6299, 2009-03-11)
.\trunk\rtl\verilog\ac97_dma_req.v (4505, 2009-03-11)
.\trunk\syn (0, 2009-03-11)
.\trunk\syn\bin (0, 2009-03-11)
.\trunk\syn\bin\read.dc (1885, 2009-03-11)
.\trunk\syn\bin\design_spec.dc (725, 2009-03-11)
.\trunk\syn\bin\comp.dc (3819, 2009-03-11)
.\trunk\syn\bin\lib_spec.dc (1120, 2009-03-11)
.\trunk\sim (0, 2009-03-11)
.\trunk\sim\rtl_sim (0, 2009-03-11)
.\trunk\sim\rtl_sim\bin (0, 2009-03-11)
.\trunk\sim\rtl_sim\bin\Makefile (2757, 2009-03-11)
.\trunk\sim\rtl_sim\run (0, 2009-03-11)
.\trunk\sim\rtl_sim\run\Makefile (2757, 2009-03-11)
... ...

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