DDRSDRAMControllerverilogcode
所属分类：VHDL/FPGA/Verilog
开发工具：Windows_Unix
文件大小：466KB
下载次数：56
上传日期：2009-03-30 23:03:54
上 传 者：
sheng.xue.fei
说明： 这个设计是使用Virtex-4实现DDR的控制器的，设计分为三个主要模块：Front-End FIFOs,DDR SDRAM Controller和Datapath Module。其中主要是DDR SDRAM Controller,当然还有测试模块。
(This design is the use of Virtex-4 implementation of the DDR controller, the design is divided into three main modules: Front-End FIFOs, DDR SDRAM Controller and Datapath Module. Are one of the main DDR SDRAM Controller, of course, have the test module.)
文件列表:
DDRSDRAMControllerverilogcode\mem_interface_top.v (3025, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_addr_gen_0.v (5114, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_backend_fifos_0.v (4570, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_backend_rom_0.v (5713, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_cmp_rd_data_0.v (6558, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_controller_iobs_0.v (3963, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_data_gen_16.v (7581, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_data_path_0.v (3881, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_data_path_iobs_0.v (57608, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_data_tap_inc.v (4020, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_data_write_0.v (4833, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_ddr_controller_0.v (54557, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_idelay_ctrl.v (1358, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_infrastructure.v (4202, 2007-09-29)
DDRSDRAMControllerverilogcode\mem_interface_top_infrastructure_iobs_0.v (4596, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_parameters_0.v (3773, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_pattern_compare8.v (6498, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_RAM_D_0.v (4598, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_rd_data_0.v (19453, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_rd_data_fifo_0.v (6672, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_rd_wr_addr_fifo_0.v (4310, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_tap_ctrl_0.v (16111, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_tap_logic_0.v (5493, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_test_bench_0.v (6736, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_user_interface_0.v (3891, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_v4_dm_iob.v (1576, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_v4_dqs_iob.v (2697, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_v4_dq_iob.v (2755, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_wr_data_fifo_16.v (2528, 2007-09-27)
DDRSDRAMControllerverilogcode\使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.pdf (639510, 2007-09-19)
DDRSDRAMControllerverilogcode\mem_interface_top_iobs_0.v (4714, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_main_0.v (5122, 2007-09-27)
DDRSDRAMControllerverilogcode\mem_interface_top_top_0.v (11119, 2007-09-27)
DDRSDRAMControllerverilogcode\使用 Virtex-4 FPGA 器件实现DDR SDRAM控制器.doc (24064, 2009-01-08)
DDRSDRAMControllerverilogcode (0, 2009-03-30)
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