CIII_NiosII_Small
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：569KB
下载次数：36
上传日期：2009-04-13 13:29:33
上 传 者：
ipvideo
说明： altera fpga ep3c25器件niosii处理器最小系统，已编译通过，可直接下载
(altera fpga ep3c25 processor minimum system niosii device has been compiled through direct download)
文件列表:
CIII_NiosII_Small\.sopc_builder\install.ptf (11692, 2009-02-27)
CIII_NiosII_Small\.sopc_builder\install2.ptf (1249, 2009-02-28)
CIII_NiosII_Small\CIII_NiosII_Small.bsf (975, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small.cdf (367, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small.done (26, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small.dpf (239, 2009-02-28)
CIII_NiosII_Small\CIII_NiosII_Small.fit.smsg (513, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small.jdi (32576, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small.pin (40390, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small.pof (2097339, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small.ptf (57040, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small.ptf.pre_generation_ptf (30527, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small.qpf (918, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small.qsf (4871, 2009-02-28)
CIII_NiosII_Small\CIII_NiosII_Small.qws (1035, 2009-02-28)
CIII_NiosII_Small\CIII_NiosII_Small.sof (703651, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small.sopc (10715, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small.v (133779, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small_assignment_defaults.qdf (33002, 2009-02-03)
CIII_NiosII_Small\CIII_NiosII_Small_generation_script (1889, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small_setup_quartus.tcl (225, 2007-04-20)
CIII_NiosII_Small\CIII_NiosII_Small_sim\dummy_file (0, 2009-02-28)
CIII_NiosII_Small\CIII_NiosII_Small_temp.ptf (6195, 2009-02-28)
CIII_NiosII_Small\CIII_NiosII_Small_temp.ptf.bak (1505, 2009-02-28)
CIII_NiosII_Small\CIII_NiosII_Small_temp.v (85, 2009-02-28)
CIII_NiosII_Small\CIII_NiosII_Small_top.bdf (4705, 2007-04-20)
CIII_NiosII_Small\cpu_0.ocp (840, 2007-04-20)
CIII_NiosII_Small\cpu_0.v (194656, 2007-04-20)
CIII_NiosII_Small\cpu_0.vo (144906, 2007-04-20)
CIII_NiosII_Small\cpu_0_jtag_debug_module.v (12393, 2007-04-20)
CIII_NiosII_Small\cpu_0_jtag_debug_module_wrapper.v (9896, 2007-04-20)
CIII_NiosII_Small\cpu_0_ociram_default_contents.mif (6153, 2007-04-20)
CIII_NiosII_Small\cpu_0_rf_ram.mif (600, 2007-04-20)
CIII_NiosII_Small\cpu_0_test_bench.v (38541, 2007-04-20)
CIII_NiosII_Small\db\CIII_NiosII_Small.db_info (137, 2009-02-03)
CIII_NiosII_Small\db\CIII_NiosII_Small.eco.cdb (161, 2009-02-28)
CIII_NiosII_Small\db\CIII_NiosII_Small.sld_design_entry.sci (154, 2009-02-28)
CIII_NiosII_Small\jtag_uart.v (22602, 2007-04-20)
CIII_NiosII_Small\led_pio.v (1898, 2007-04-20)
CIII_NiosII_Small\name_err.log (0, 2007-04-20)
... ...
readme - Cyclone III Starter Kit - Nios II Small Design
Overview:
This design is provided for Cyclone III Starter Kit boards and demonstrates an example of a small functional Nios II system.
Contents of the System:
- Nios II/e Core
- LED PIO
- On chip memory
- JTAG UART (Can be removed to make design smaller)
Hardware Specs:
- Fmax > 101.57MHz
- Resource Usage = 1309 LEs (5%)
- Onchip Memory Usage = 16KB
Supported Software Examples:
- Blank Project
- Hello World Small
- Hello LED
Further notes:
- The top level of this design is BDF. The top level BDF is a wrapper around the SOPC Builder design symbol block.
If you modify and regenerate the SOPC Builder design, the port list of the SOPC Builder instance may change.
You must manually edit the BDF pin assignments to make certain they are properly attached to the symbol block.
to rectify any discrepancies.
- This Quartus project contains assignments that match the port names produced by SOPC Builder.
If you add or edit in SOPC Builder components, the pin assignments may no longer be applied.
To see the assignments in Quartus, go to the Assignments menu, click "Assignment Editor".
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