pcie_vera_tb_latest.tar
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：166KB
下载次数：50
上传日期：2009-04-17 13:58:23
上 传 者：
realsmart
说明： FEATURES
• 16 bit PIPE Spec PCI Express Testbench
• Link training
• Initial Flow Control
• Packet Classes for easy to build PHY,DLLP and TLP packets
• DLLP 16 bit CRC and TLP LCRC generation
• Sequence Number generation and checking
• ACK TLP packets
• Scrambling
• MemRd MemWr CfgRd CfgWr TLPs
文件列表:
.\trunk (0, 2009-03-11)
.\trunk\scramble8.vri (2592, 2009-03-11)
.\trunk\ti_phy_top.if.vrh (2853, 2009-03-11)
.\trunk\send_packet.vri (3227, 2009-03-11)
.\trunk\docs (0, 2009-03-11)
.\trunk\docs\PCI_Express_VERA_testbench.pdf (157413, 2009-03-11)
.\trunk\ti_phy_top.vr (6022, 2009-03-11)
.\trunk\skip_order_set.vri (2109, 2009-03-11)
.\trunk\pcie_tlp_packet.vri (24699, 2009-03-11)
.\trunk\InitFC1.vri (15794, 2009-03-11)
.\trunk\pcie_phy_packet.vri (3272, 2009-03-11)
.\trunk\link_training.vri (6494, 2009-03-11)
.\trunk\tlp_gen.vri (14432, 2009-03-11)
.\trunk\run_vera (341, 2009-03-11)
.\trunk\pcie_dllp_packet.vri (6967, 2009-03-11)
.\trunk\ti_phy_top.v (6576, 2009-03-11)
.\trunk\ti_phy_top.test_top.v (9092, 2009-03-11)
.\trunk\receive_packet.vri (11551, 2009-03-11)
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