add
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：13KB
下载次数：6
上传日期：2009-04-25 12:53:21
上 传 者：
357127465
说明： 一位全加器源码实现了MAX及其一系列器件实现全加的功能
(A full adder and its source code to achieve the MAX series of devices to achieve the functions of the All-Canadian)
文件列表:
add\add.acf (15649, 2009-04-08)
add\add.cnf (2361, 2009-04-08)
add\add.fit (2161, 2009-04-08)
add\add.hif (1604, 2009-04-15)
add\add.mmf (236, 2009-04-08)
add\add.ndb (664, 2009-04-08)
add\add.pin (3518, 2009-04-08)
add\add.pof (1961, 2009-04-08)
add\add.rpt (11286, 2009-04-08)
add\add.scf (106, 2009-04-08)
add\add.snf (2003, 2009-04-08)
add\ADD.sym (253, 2009-04-08)
add\add.vhd (276, 2009-03-21)
add\LIB.DLS (111, 2009-04-08)
add\U2103917.DLS (2556, 2009-04-08)
add\U7065527.DLS (988, 2009-04-08)
add\U7857163.DLS (1144, 2009-04-08)
add (0, 2009-04-08)
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