fdiv
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：179KB
下载次数：16
上传日期：2009-04-29 01:17:18
上 传 者：
nazhenaxuan
说明： 基于Quartus II的数控分频器的项目设计，实现对时钟信号的任意进制分频，包含了项目文件和VHDL源代码
(NC-based prescaler Quartus II project design, implementation of the clock signal of arbitrary frequency band, including the project files and VHDL source code)
文件列表:
fdiv\db\DVF.(0).cnf.cdb (1696, 2009-04-17)
fdiv\db\DVF.(0).cnf.hdb (706, 2009-04-17)
fdiv\db\DVF.asm.qmsg (1821, 2009-04-23)
fdiv\db\DVF.cbx.xml (85, 2009-04-23)
fdiv\db\DVF.cmp.bpm (458, 2009-04-23)
fdiv\db\DVF.cmp.cdb (5110, 2009-04-23)
fdiv\db\DVF.cmp.ecobp (28, 2009-04-23)
fdiv\db\DVF.cmp.hdb (6830, 2009-04-23)
fdiv\db\DVF.cmp.logdb (4, 2009-04-23)
fdiv\db\DVF.cmp.rdb (16176, 2009-04-23)
fdiv\db\DVF.cmp.tdb (4679, 2009-04-23)
fdiv\db\DVF.cmp0.ddb (19103, 2009-04-23)
fdiv\db\DVF.cmp_bb.cdb (2987, 2009-04-23)
fdiv\db\DVF.cmp_bb.hdb (6700, 2009-04-23)
fdiv\db\DVF.cmp_bb.logdb (4, 2009-04-23)
fdiv\db\DVF.cmp_bb.rcf (1280, 2009-04-23)
fdiv\db\DVF.dbp (0, 2009-04-23)
fdiv\db\DVF.db_info (137, 2009-04-17)
fdiv\db\DVF.eco.cdb (161, 2009-04-23)
fdiv\db\DVF.eds_overflow (5, 2009-04-23)
fdiv\db\DVF.fit.qmsg (25150, 2009-04-23)
fdiv\db\DVF.hier_info (470, 2009-04-23)
fdiv\db\DVF.hif (731, 2009-04-23)
fdiv\db\DVF.map.bpm (456, 2009-04-23)
fdiv\db\DVF.map.cdb (2042, 2009-04-23)
fdiv\db\DVF.map.ecobp (28, 2009-04-23)
fdiv\db\DVF.map.hdb (6493, 2009-04-23)
fdiv\db\DVF.map.logdb (4, 2009-04-23)
fdiv\db\DVF.map.qmsg (3662, 2009-04-23)
fdiv\db\DVF.map_bb.cdb (1991, 2009-04-23)
fdiv\db\DVF.map_bb.hdb (6493, 2009-04-23)
fdiv\db\DVF.map_bb.logdb (4, 2009-04-23)
fdiv\db\DVF.pre_map.cdb (1709, 2009-04-23)
fdiv\db\DVF.pre_map.hdb (6525, 2009-04-23)
fdiv\db\DVF.psp (3, 2009-04-23)
fdiv\db\DVF.pss (36, 2009-04-23)
fdiv\db\DVF.rtlv.hdb (6518, 2009-04-23)
fdiv\db\DVF.rtlv_sg.cdb (1634, 2009-04-23)
fdiv\db\DVF.rtlv_sg_swap.cdb (178, 2009-04-23)
fdiv\db\DVF.sgdiff.cdb (1520, 2009-04-23)
... ...
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