UpDownCounter
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：406KB
下载次数：16
上传日期：2009-04-29 04:48:00
上 传 者：
ash_bladerunner
说明： an up down counter in verilog
文件列表:
bistabil.v (182, 2007-05-06)
counter4bCuCunterulNormal.JPG (127028, 2007-05-06)
counter.jpg (113126, 2007-05-02)
counterPart1.v (688, 2007-05-08)
counterPart2.v (1478, 2007-05-08)
counterPart3.v (1926, 2007-05-08)
counterPorti.v (2257, 2007-05-08)
counterPorti_tb.v (633, 2007-05-08)
counterPorti_test.v (1046, 2007-05-08)
DW03_bictr_dcnto.pdf (59625, 2007-04-12)
mux21.v (107, 2007-05-06)
pozna2.JPG (79783, 2007-05-02)
pozna3.JPG (108679, 2007-05-02)
pozna4.JPG (111542, 2007-05-02)
pozna.JPG (8642, 2007-05-02)
schema synplify.JPG (69458, 2007-05-05)
sumator1bit.v (355, 2007-05-06)
sumator1bitNoCarryIn.v (270, 2007-05-06)
sumator1bitNoCarryOut.v (263, 2007-05-06)
test.v (1203, 2007-05-08)
transcript (278, 2007-05-23)
UDCounter.v (987, 2007-05-02)
UDCounter_tb.v (628, 2007-05-06)
UDCounter_test.v (784, 2007-05-06)
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