PLL
所属分类：VHDL/FPGA/Verilog
开发工具：Others
文件大小：124KB
下载次数：39
上传日期：2009-05-01 20:10:43
上 传 者：
xwaly
说明： PLL是数字锁相环设计源程序,
其中, Fi是输入频率(接收数据),
Fo(Q5)是本地输出频率.
目的是从输入数据中提取时钟信号(Q5),
其频率与数据速率一致,
时钟上升沿锁定在数据的上升和下降沿上；
顶层文件是PLL.GDF
(Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is a local output frequency. The purpose is to extract data from the input clock signal (Q5), their frequency and data rate in line clock rising edge of lock-in data on rising and falling edge PLL.GDF top-level document)
文件列表:
Digital phase-locked loop PLL\dpll.gdf (5659, 2004-12-09)
Digital phase-locked loop PLL\edge.gdf (1638, 2004-12-09)
Digital phase-locked loop PLL\edge.sym (192, 2004-12-09)
Digital phase-locked loop PLL\fenpin.sym (297, 2004-12-08)
Digital phase-locked loop PLL\fenpin.v (550, 2004-12-08)
Digital phase-locked loop PLL\pll\aa.gdf (2606, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.acf (15768, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.cnf (1829, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.fit (2201, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.gdf (1633, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.hex (34004, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.hif (1570, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.mmf (538, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.ndb (559, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.pin (5235, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.pof (55238, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.rpt (18808, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.scf (625, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.snf (2212, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.sof (14430, 2003-07-07)
Digital phase-locked loop PLL\pll\edge.ttf (59691, 2003-07-07)
Digital phase-locked loop PLL\pll\inst1.gdf (3969, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.acf (15767, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.cnf (2986, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.fit (2591, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.gdf (3969, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.hex (34004, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.hif (1578, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.mmf (542, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.ndb (795, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.pin (5237, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.pof (55240, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.rpt (19404, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.scf (1218, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.snf (4377, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.sof (14430, 2003-07-07)
Digital phase-locked loop PLL\pll\mealy1.ttf (59691, 2003-07-07)
Digital phase-locked loop PLL\pll\pll(1).cnf (7173, 2003-07-07)
Digital phase-locked loop PLL\pll\pll(2).cnf (4316, 2003-07-07)
Digital phase-locked loop PLL\pll\pll(3).cnf (4923, 2003-07-07)
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