文件列表:

xapp615 (0, 2009-04-26)
xapp615\iquant_v.v (36619, 2003-02-14)
xapp615\iquant_vhd.vhd (39881, 2003-03-05)
xapp615\quant_v.v (50422, 2003-02-18)
xapp615\quant_vhd.vhd (54842, 2003-03-05)

********************************************************************** ** Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are ** provided to you "as is". Xilinx and its licensors make and you ** receive no warranties or conditions, express, implied, ** statutory or otherwise, and Xilinx specifically disclaims any ** implied warranties of merchantability, non-infringement,or ** fitness for a particular purpose. Xilinx does not warrant that ** the functions contained in these designs will meet your ** requirements, or that the operation of these designs will be ** uninterrupted or error free, or that defects in the Designs ** will be corrected. Furthermore, Xilinx does not warrantor ** make any representations regarding use or the results of the ** use of the designs in terms of correctness, accuracy, ** reliability, or otherwise. ** ** LIMITATION OF LIABILITY. In no event will Xilinx or its ** licensors be liable for any loss of data, lost profits,cost ** or procurement of substitute goods or services, or for any ** special, incidental, consequential, or indirect damages ** arising from the use or operation of the designs or ** accompanying documentation, however caused and on any theory ** of liability. This limitation will apply even if Xilinx ** has been advised of the possibility of such damage. This ** limitation shall apply not-withstanding the failure of the ** essential purpose of any limited remedies herein. ** ** Copyright (c) 2003 Xilinx, Inc. ** All rights reserved ** ****************************************************************************** XAPP615 Zip file contains The word document Verilog files (*.v) quant_v.v iquant_v.v Vhdl file (*.vhd) quant_vhd.vhd iquant_vhd.vhd The verilog and vhdl synthesized and places and routed using Foundation 5.1.03I. Synplify Pro Verilog was used for synthesis.

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