up_convert
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：21KB
下载次数：105
上传日期：2009-05-09 09:48:22
上 传 者：
xuexifpga
说明： vhdl硬件设计实现一个数字上变频器，实现数字上变频
(vhdl hardware design on the realization of a digital converter, digital up-conversion)
文件列表:
up_convert\ddc.vhdl (2291, 2009-05-04)
up_convert\ddc.xml (751, 2009-05-05)
up_convert\ddc_counter.vhdl (908, 2009-05-04)
up_convert\ddc_tb.vhd.bak (1103, 2009-05-05)
up_convert\ddc_tb.vhdl (1962, 2009-05-07)
up_convert\ddc_tb.vhdl.bak (1907, 2009-05-07)
up_convert\modelsim.ini (18625, 2009-05-04)
up_convert\test.v (455, 2009-05-05)
up_convert\test.v.bak (440, 2009-05-05)
up_convert\work\ddc\duc_cos_arch.asm (7098, 2009-05-07)
up_convert\work\ddc\duc_cos_arch.dat (1038, 2009-05-07)
up_convert\work\ddc\_primary.dat (383, 2009-05-07)
up_convert\work\ddc_counter\rtl.asm (2803, 2009-05-07)
up_convert\work\ddc_counter\rtl.dat (369, 2009-05-07)
up_convert\work\ddc_counter\_primary.dat (269, 2009-05-07)
up_convert\work\ddc_tb\ddc_tb_arch.asm (5956, 2009-05-07)
up_convert\work\ddc_tb\ddc_tb_arch.dat (1180, 2009-05-07)
up_convert\work\ddc_tb\_primary.dat (128, 2009-05-07)
up_convert\work\test\verilog.asm (6056, 2009-05-05)
up_convert\work\test\_primary.dat (662, 2009-05-05)
up_convert\work\test\_primary.vhd (68, 2009-05-05)
up_convert\work\_info (1894, 2009-05-07)
up_convert\work\ddc (0, 2009-05-04)
up_convert\work\ddc_counter (0, 2009-05-04)
up_convert\work\ddc_tb (0, 2009-05-05)
up_convert\work\test (0, 2009-05-04)
up_convert\work (0, 2009-05-07)
up_convert (0, 2009-05-06)
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