xapp610
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：125KB
下载次数：194
上传日期：2009-05-25 22:13:43
上 传 者：
whitestone
说明： Verilog code for 2D-DCT with detailed documentation.
文件列表:
dct-idct.v (537, 2002-01-29)
test_dct.v (4980, 2002-01-29)
dct.doc (146944, 2002-01-31)
dct.v (33613, 2003-09-08)
dct.vhd (38702, 2003-09-08)
dct.pdf (68960, 2009-05-03)
XAPP610 Zip file contains
The word document for DCT
Verilog files (*.v)
dct.v
test_dct.v
Vhdl file (*.vhd)
dct.vhd
The verilog synthesized using Synplicity (Synplify Pro) and placed and routed using Foundation 4.1.03i.
The multiplier instantiation in the verilog files are used when targeting Virtex 2. For all other devices,
the instantiations are commented out and the behavioral multiplier code is used. Test_dct contains the
test bench which uses the input values as given in the reference "Image and Video Compression Standards"
by V. Bhaskaran and K. Konstantinides. Dct-dct.v is the top level file that calls the lower level dct.v
and idct.v files. The lower level vhdl files are dct.vhd and idct.vhd
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