EP1C3_12_10_PHAS
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：48KB
下载次数：49
上传日期：2009-05-27 20:55:02
上 传 者：
deadtomb
说明： 基于FPGA的移相式DDS正弦信号发生器的VHDL源代码，压缩包里是在Quartus里做的工程，FPGA用的是Cyclone1C3系列
(FPGA-based phase-shifting of the DDS signal generator sine VHDL source code, compressed in the bag is done in Quartus Engineering, FPGA is used Cyclone1C3 Series)
文件列表:
EP1C3_12_10_PHAS\ADDER10B.VHD (349, 2009-04-21)
EP1C3_12_10_PHAS\ADDER32B.VHD (350, 2009-04-21)
EP1C3_12_10_PHAS\cmp_state.ini (2, 2009-04-21)
EP1C3_12_10_PHAS\dds_vhdl.asm.rpt (9343, 2009-04-21)
EP1C3_12_10_PHAS\DDS_VHDL.CDF (333, 2009-04-21)
EP1C3_12_10_PHAS\dds_vhdl.done (26, 2009-04-21)
EP1C3_12_10_PHAS\dds_vhdl.fit.summary (395, 2009-04-21)
EP1C3_12_10_PHAS\dds_vhdl.flow.rpt (4092, 2009-04-21)
EP1C3_12_10_PHAS\dds_vhdl.map.summary (333, 2009-04-21)
EP1C3_12_10_PHAS\DDS_VHDL.PIN (19982, 2009-04-21)
EP1C3_12_10_PHAS\DDS_VHDL.QPF (1561, 2009-04-21)
EP1C3_12_10_PHAS\DDS_VHDL.QSF (16009, 2009-04-21)
EP1C3_12_10_PHAS\DDS_VHDL.QWS (1793, 2009-04-21)
EP1C3_12_10_PHAS\DDS_VHDL.SOF (74117, 2009-04-21)
EP1C3_12_10_PHAS\dds_vhdl.tan.summary (3152, 2009-04-21)
EP1C3_12_10_PHAS\DDS_VHDL.VHD (2617, 2009-04-21)
EP1C3_12_10_PHAS\dds_vhdl_assignment_defaults.qdf (29362, 2009-04-21)
EP1C3_12_10_PHAS\PLL20.VHD (9699, 2009-04-21)
EP1C3_12_10_PHAS\REG10B.VHD (441, 2009-04-21)
EP1C3_12_10_PHAS\REG32B.VHD (441, 2009-04-21)
EP1C3_12_10_PHAS\SIN_ROM.VHD (6554, 2009-04-21)
EP1C3_12_10_PHAS\STP1.STP (31901, 2009-04-21)
EP1C3_12_10_PHAS\DATA\LUT10X10.HEX (17421, 2009-04-21)
EP1C3_12_10_PHAS\DATA\LUT10X10.MIF (15191, 2009-04-21)
EP1C3_12_10_PHAS\DATA (0, 2009-05-27)
EP1C3_12_10_PHAS (0, 2009-05-27)
近期下载者：
相关文件：
收藏者：