EP1C3_12_5_RSV
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：60KB
下载次数：213
上传日期：2009-05-27 20:58:46
上 传 者：
deadtomb
说明： 基于ＦＰＧＡ的数字存储示波器，用ＶＨＤＬ实现的，压缩包里是Quartus工程。AD采样送进FPGA，存入SRAM后用DA在普通示波器上可以显示。
(FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinary oscilloscope can display.)
文件列表:
EP1C3_12_5_RSV\cmp_state.ini (2, 2009-04-21)
EP1C3_12_5_RSV\dp.cmp (1289, 2009-04-21)
EP1C3_12_5_RSV\dp.vhd (10809, 2009-04-21)
EP1C3_12_5_RSV\dpr.cmp (1294, 2009-04-21)
EP1C3_12_5_RSV\dpr.vhd (10974, 2009-04-21)
EP1C3_12_5_RSV\DPRAM.VHD (7822, 2009-04-21)
EP1C3_12_5_RSV\RESERV.ACF (14814, 2009-04-21)
EP1C3_12_5_RSV\RESERV.asm.rpt (9225, 2009-04-21)
EP1C3_12_5_RSV\RESERV.CDF (325, 2009-04-21)
EP1C3_12_5_RSV\RESERV.done (26, 2009-04-21)
EP1C3_12_5_RSV\RESERV.fit.summary (391, 2009-04-21)
EP1C3_12_5_RSV\RESERV.flow.rpt (4074, 2009-04-21)
EP1C3_12_5_RSV\RESERV.HIF (1518, 2009-04-21)
EP1C3_12_5_RSV\RESERV.map.rpt (100478, 2009-04-21)
EP1C3_12_5_RSV\RESERV.map.summary (329, 2009-04-21)
EP1C3_12_5_RSV\RESERV.PIN (19980, 2009-04-21)
EP1C3_12_5_RSV\RESERV.QPF (1559, 2009-04-21)
EP1C3_12_5_RSV\RESERV.QSF (3929, 2009-04-21)
EP1C3_12_5_RSV\RESERV.QWS (2552, 2009-04-21)
EP1C3_12_5_RSV\RESERV.SOF (74117, 2009-04-21)
EP1C3_12_5_RSV\RESERV.tan.summary (3192, 2009-04-21)
EP1C3_12_5_RSV\RESERV.VHD (1038, 2009-04-21)
EP1C3_12_5_RSV\RESERV_assignment_defaults.qdf (29362, 2009-04-21)
EP1C3_12_5_RSV\RRR.VHD (5322, 2009-04-21)
EP1C3_12_5_RSV\STP1.STP (44362, 2009-04-21)
EP1C3_12_5_RSV\DATA\LUT8X10.HEX (15373, 2009-04-21)
EP1C3_12_5_RSV\DATA\LUT8X10.MIF (14797, 2009-04-21)
EP1C3_12_5_RSV\db\RESERV.db_info (136, 2009-04-21)
EP1C3_12_5_RSV\db\RESERV.eco.cdb (141, 2009-04-21)
EP1C3_12_5_RSV\DATA (0, 2009-05-27)
EP1C3_12_5_RSV\db (0, 2009-05-27)
EP1C3_12_5_RSV (0, 2009-05-27)
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