soc-gr0040-010309
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：397KB
下载次数：10
上传日期：2009-05-29 23:59:39
上 传 者：
urga
说明： xsoc vhdl verilog risc cpu soc implementation in very liitle cpld or fpga
文件列表:
LICENSE (5762, 2001-03-09)
soc-gr0040-slides.pdf (269051, 2001-03-09)
soc-gr0040-paper.pdf (179954, 2001-03-09)
soc-gr0040.v (19243, 2001-03-09)
soc-gr-tb.v (2201, 2001-03-09)
ramb4.v (1096, 2001-03-09)
fib.c (448, 2001-03-09)
fib.s (358, 2001-03-09)
sim-gr0.s (417, 2001-03-09)
end.s (180, 2001-03-09)
fib.lst (3298, 2001-03-09)
ramh.mem (144, 2001-03-09)
raml.mem (138, 2001-03-09)
sim.out (37293, 2001-03-09)
The soc/gr0040 Kit README
Version 2001.03.09
Copyright (C) 2001, Gray Research LLC. All rights reserved.
The contents of this file are subject to the XSOC License Agreement;
you may not use this file except in compliance with this Agreement.
See the LICENSE file.
CONTENTS
The soc/gr0040 Kit consists of these files.
1. Documentation
README: this file
LICENSE: XSOC License Agreement, also www.fpgacpu.org/xsoc/LICENSE.html
soc-gr0040-paper.pdf: DesignCon 2001 paper: "Designing a Simple
FPGA-Optimized RISC CPU and System-on-a-Chip"
soc-gr0040-slides.pdf: Accompanying slides
2. Verilog Design
soc-gr0040.v: the gr0040 and gr0041 processors and system-on-a-chip
soc-gr-tb.v: simple test bench
ramb4.v: block RAM simulation model
3. Demo
fib.c: simple Fibonacci sequence
fib.s: compiler output
sim-gr0.s: simple startup code and interrupt handler
end.s: simulator epilog
fib.lst, fib.hex: assembler output
ramh.mem, raml.mem: intialized block RAM memory images
Note: the design herein is Copyright (C) 2000-2001, Gray Research LLC,
and, as with the XSOC Project, is licensed only for limited
non-commercial research and academic uses, as described in the LICENSE.
Note: As of version 2001.03.09, this design runs fine in simulation,
but has not been verified in hardware.
Questions? Discuss the design on the FPGA CPU mailing list,
fpga-cpu@yahoogroups.com
Jan Gray,
President, Gray Research LLC
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