03.EDK8.2
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:22287KB
下载次数:127
上传日期:2009-05-30 16:47:15
上 传 者:
xss0303
说明: 使用xilinx virtex4芯片,设计环境为EDK,其中包含uart,片外sram操作,flash操作,DDR SDRAM操作,MAC自发自收,audio,video等试验
(Xilinx virtex4 use chip design environment for the EDK, which contains the uart, chip sram operation, flash operation, DDR SDRAM operation, MAC spontaneous self-admission, audio, video and other tests)
文件列表:
03.EDK8.2\source\lab5.c (3219, 2008-09-25)
03.EDK8.2\source\lab5.c.bak (3569, 2008-09-25)
03.EDK8.2\labsolutions\lab6\_impact.cmd (133, 2008-09-25)
03.EDK8.2\labsolutions\lab6\_impactbatch.log (3730, 2008-09-25)
03.EDK8.2\labsolutions\lab6\bitinit.log (4826, 2008-09-25)
03.EDK8.2\labsolutions\lab6\lab6.cpj (50781, 2008-09-25)
03.EDK8.2\labsolutions\lab6\libgen.log (9849, 2008-09-25)
03.EDK8.2\labsolutions\lab6\param.opt (510, 2008-09-25)
03.EDK8.2\labsolutions\lab6\platgen.log (11104, 2008-09-25)
03.EDK8.2\labsolutions\lab6\platgen.opt (47, 2008-09-25)
03.EDK8.2\labsolutions\lab6\system.bsb (2094, 2008-09-25)
03.EDK8.2\labsolutions\lab6\system.log (624504, 2008-09-25)
03.EDK8.2\labsolutions\lab6\system.make (8843, 2008-09-25)
03.EDK8.2\labsolutions\lab6\system.mhs (5321, 2008-09-25)
03.EDK8.2\labsolutions\lab6\system.mss (1897, 2008-09-25)
03.EDK8.2\labsolutions\lab6\system.xmp (2006, 2008-09-25)
03.EDK8.2\labsolutions\lab6\system_incl.make (7043, 2008-09-25)
03.EDK8.2\labsolutions\lab6\wizlog (0, 2008-09-25)
03.EDK8.2\labsolutions\lab6\xdsgen.log (304, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\chipscope_icon_0_wrapper.lso (30, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\chipscope_icon_0_wrapper_xst.prj (164, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\chipscope_icon_0_wrapper_xst.scr (253, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\chipscope_icon_0_wrapper_xst.srp (9773, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\chipscope_opb_iba.lso (19, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\chipscope_opb_iba_0_wrapper.lso (6, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\chipscope_opb_iba_0_wrapper_xst.prj (50, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\chipscope_opb_iba_0_wrapper_xst.scr (262, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\chipscope_opb_iba_0_wrapper_xst.srp (28781, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\cs_edk_port_mapper_chipscope_opb_iba_0_xst.prj (97, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\cs_edk_port_mapper_chipscope_opb_iba_0_xst.scr (297, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\cs_edk_port_mapper_chipscope_opb_iba_0_xst.srp (15833, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\dcm_0_wrapper.lso (26, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\dcm_0_wrapper_xst.prj (142, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\dcm_0_wrapper_xst.scr (220, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\dcm_0_wrapper_xst.srp (11625, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\debug_module_wrapper.lso (44, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\debug_module_wrapper_xst.prj (745, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\debug_module_wrapper_xst.scr (241, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\debug_module_wrapper_xst.srp (28309, 2008-09-25)
03.EDK8.2\labsolutions\lab6\synthesis\delay_wrapper.lso (46, 2008-09-25)
... ...
TABLE OF CONTENTS
1) Peripheral Summary
2) Description of Generated Files
3) Description of Used IPIC Signals
4) Description of Top Level Generics
================================================================================
* 1) Peripheral Summary *
================================================================================
Peripheral Summary:
XPS project / EDK repository : D:\02.EDK8.2\labs\lab3
logical library name : my_led_v1_00_a
top name : my_led
version : 1.00.a
type : OPB slave
features : slave attachement
mir/rst register
user s/w registers
Address Block for User Logic and IPIF Predefined Services
User logic slave space service : C_BASEADDR + 0x00000000
: C_BASEADDR + 0x000000FF
IPIF Reset/MIR service : C_BASEADDR + 0x00000100
: C_BASEADDR + 0x000001FF
================================================================================
* 2) Description of Generated Files *
================================================================================
- HDL source file(s)
D:\02.EDK8.2\labs\lab3/pcores/my_led_v1_00_a/hdl
vhdl/my_led.vhd
This is the template file for your peripheral's top design entity. It
configures and instantiates the corresponding IPIF unit in the way you
indicated in the wizard GUI and hooks it up to the stub user logic where
the actual functionalites should get implemented. You are not expected to
modify this template file except certain marked places for adding user
specific generics and ports.
vhdl/user_logic.vhd
This is the template file for the stub user logic design entity, either in
VHDL or Verilog, where the actual functionalities should get implemented.
Some sample code snippet may be provided for demonstration purpose.
- XPS interface file(s)
D:\02.EDK8.2\labs\lab3/pcores/my_led_v1_00_a/data
my_led_v2_1_0.mpd
This Microprocessor Peripheral Description file contains information of the
interface of your peripheral, so that other EDK tools can recognize your
peripheral.
my_led_v2_1_0.pao
This Peripheral Analysis Order file defines the analysis order of all the HDL
source files that are used to compile your peripheral.
- Driver source file(s)
D:\02.EDK8.2\labs\lab3/drivers/my_led_v1_00_a/src
my_led.h
This is the software driver header template file, which contains address offset of
software addressable registers in your peripheral, as well as some common masks and
simple register access macros or function declaration.
my_led.c
This is the software driver source template file, to define all applicable driver
functions.
my_led_selftest.c
This is the software driver self test example file, which contain self test example
code to test various hardware features of your peripheral.
Makefile
This is the software driver makefile to compile drivers.
- Driver interface file(s)
D:\02.EDK8.2\labs\lab3/drivers/my_led_v1_00_a/data
my_led_v2_1_0.mdd
This is the Microprocessor Driver Definition file.
my_led_v2_1_0.tcl
This is the Microprocessor Driver Command file.
- Other misc file(s)
D:\02.EDK8.2\labs\lab3/pcores/my_led_v1_00_a/devl
ipwiz.opt
This is the option setting file for the wizard batch mode, which should
generate the same result as the wizard GUI mode.
README.txt
This README file for your peripheral.
ipwiz.log
This is the log file by operating on this wizard.
================================================================================
* 3) Description of Used IPIC Signals *
================================================================================
For more information (usage, timing diagrams, etc.) regarding the IPIC signals
used in the templates, please refer to the following specifications (under
%XILINX_EDK%\doc for windows or $XILINX_EDK/doc for solaris and linux):
proc_ip_ref_guide.pdf - Processor IP Reference Guide (chapter 4 IPIF)
user_core_templates_ref_guide.pdf - User Core Templates Reference Guide
Bus2IP_Clk
This is the clock input to the user logic. All IPIC signals are synchronous
to this clock. It is identical to the _Clk signal that is an input to
the user core. In an OPB core, Bus2IP_Clk is the same as OPB_Clk, and in a
PLB core, it is the same as PLB_Clk. No additional buffering is provided on
the clock; it is passed through as is.
Bus2IP_Reset
Signal to reset the User Logic; asserts whenever the _Rst signal does
and, if the Reset block is included, whenever there is a software-programmed
reset.
Bus2IP_Data
This is the data bus from the IPIF to the user logic; it is used for both
master and slave transactions. It is used to access user logic registers.
Bus2IP_BE
The Bus2IP_BE is a bus of Byte Enable qualifiers from the IPIF to the user
logic. A bit in the Bus2IP_BE set to '1' indicates that the associated byte
lane contains valid data. For example, if Bus2IP_BE = 0011, this indicates
that byte lanes 2 and 3 contains valid data.
Bus2IP_RdCE
The Bus2IP_RdCE bus is an input to the user logic. It is Bus2IP_CE qualified
by a read transaction.
Bus2IP_WrCE
The Bus2IP_WrCE bus is an input to the user logic. It is Bus2IP_CE qualified
by a write transaction.
IP2Bus_Data
This is the data bus from the user logic to the IPIF; it is used for both
master and slave transactions. It is used to access user logic registers.
IP2Bus_Ack
The IP2Bus_Ack signal provide the read/write acknowledgement from the user
logic to the IPIF. For writes, it indicates the data has been taken by the
user logic. For reads, it indicates that valid data is available. For
immediate acknowledgement (such as for a register read/write), this signal
can be tied to '1'. Wait states can be inserted in the transaction by
delaying the assertion of the acknowledgement. If the IP2Bus_Ack for OPB
cores will be delayed more than 8 clocks, then the IP2Bus_ToutSup (timeout
suppress) signal must also be asserted to prevent a timeout on the host bus.
IP2Bus_Retry
IP2Bus_Retry is a response from the user logic to the IPIF that indicates
the currently requested transaction cannot be completed at this time and
that the requesting master should retry the operation. If the IP2Bus_Retry
signal will be delayed more than 8 clocks, then the IP2Bus_ToutSup (timeout
suppress) signal must also be asserted to prevent a timeout on the host bus.
Note: this signal is unused by PLB IPIF.
IP2Bus_Error
This signal from the user logic to the IPIF indicates an error has occurred
during the current transaction. It is valid when IP2Bus_Ack is asserted.
IP2Bus_ToutSup
The IP2Bus_ToutSup must be asserted by the user logic whenever its
acknowledgement or retry response will take longer than 8 clock cycles.
================================================================================
* 4) Description of Top Level Generics *
================================================================================
C_BASEADDR/C_HIGHADDR
These two generics are used to define the memory mapped address space for
the peripheral registers, including Reset/MIR register, Interrupt Source
Controller registers, Read/Write FIFO control/data registers, user logic
software accessible registers and etc., but excluding those user logic
address ranges if ever used. When instantiation, the address space size
determined by these two generics must be a power of 2 (e.g. 2^k =
C_HIGHADDR - C_BASEADDR + 1), a factor of C_BASEADDR and larger than the
minimum size as indicated in the template.
C_OPB_DWIDTH
This is the data bus width for On-chip Peripheral Bus (OPB). It should
always be set to 32 as of today.
C_OPB_AWIDTH
This is the address bus width for On-chip Peripheral Bus (OPB). It should
always be set to 32 as of today.
C_USER_ID_CODE
This is the ID that will be put into the MIR register, it's mainly used
for debug purpose to identify the peripheral under test if multiple
instances exist in the system.
C_FAMILY
This is to set the target FPGA architecture, s.t. virtex2, virtex2p, etc.
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