sdram
所属分类：其他
开发工具：Others
文件大小：154KB
下载次数：11
上传日期：2009-06-01 14:46:48
上 传 者：
twinsis
说明： 在ISE开发环境下的单速率SDRAM简单读写控制器设计，用的是verilog硬件描述语言
(ISE development environment in a single-rate SDRAM controller read and write simple design, using the verilog hardware description language)
文件列表:
test\ise\automake.log (0, 2009-04-16)
test\ise\coregen.log (635, 2009-04-16)
test\ise\coregen.prj (7472, 2006-01-18)
test\ise\fpga.cmd_log (1539, 2006-01-20)
test\ise\fpga.lso (6, 2006-01-20)
test\ise\fpga.ngc (63532, 2006-01-20)
test\ise\fpga.ngr (99869, 2006-01-20)
test\ise\fpga.prj (28, 2006-01-20)
test\ise\fpga.stx (0, 2006-01-20)
test\ise\fpga.syr (18041, 2006-01-20)
test\ise\fpga_top.lso (22, 2009-04-16)
test\ise\fpga_top.prj (26, 2009-04-16)
test\ise\fpga_top.sch (252, 2009-04-16)
test\ise\fpga_top.stx (615, 2009-04-16)
test\ise\fpga_top.sym (205, 2009-04-16)
test\ise\fpga_top.tfi (256, 2009-04-16)
test\ise\fpga_top.vf (140, 2009-04-16)
test\ise\fpga_top_vhdl.prj (0, 2009-04-16)
test\ise\fpga_vhdl.prj (0, 2006-01-20)
test\ise\prjname.lso (6, 2009-04-16)
test\ise\test.dhp (2089, 2009-04-16)
test\ise\test.npl (534, 2009-04-16)
test\ise\top.sch (252, 2009-04-16)
test\ise\top.sym (205, 2009-04-16)
test\ise\xst\work\hdllib.ref (92, 2009-04-16)
test\ise\xst\work\vlg22\fpga.bin (26969, 2006-01-20)
test\ise\xst\work\vlg54\fpga_top.bin (237, 2009-04-16)
test\ise\__projnav\coregen.rsp (111, 2009-04-16)
test\ise\__projnav\fpga.xst (955, 2006-01-20)
test\ise\__projnav\fpga_top.xst (58, 2009-04-16)
test\ise\__projnav\fpga_top_jhdparse_tcl.rsp (32, 2009-04-16)
test\ise\__projnav\runXst_tcl.rsp (32, 2006-01-20)
test\ise\__projnav\test.gfl (4270, 2009-04-16)
test\ise\__projnav\test_flowplus.gfl (2962, 2009-04-16)
test\ise\__projnav\top_jhdparse_tcl.rsp (27, 2009-04-16)
test\ise\__projnav\xst_sprjTOstx_tcl.rsp (36, 2009-04-16)
test\ise\__projnav.log (190581, 2009-04-16)
test\modelsim\test.cr.mti (649, 2006-01-20)
test\modelsim\test.mpf (16887, 2006-01-20)
test\modelsim\vsim.wlf (32768, 2006-01-19)
... ...
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