文件列表:

SW_CODEC\modelsim\.list (523, 2009-06-28)
SW_CODEC\modelsim\compiler.scr (53, 2009-06-28)
SW_CODEC\modelsim (0, 2009-06-28)
SW_CODEC\netlist\codec_rev_fifo.ngc (138436, 2008-04-14)
SW_CODEC\netlist\codec_tx_fifo.ngc (128671, 2008-04-14)
SW_CODEC\netlist (0, 2009-06-28)
SW_CODEC\src\codec_pkg.vhd (2078, 2009-06-28)
SW_CODEC\src\codec_rev_fifo.vhd (5554, 2008-04-14)
SW_CODEC\src\codec_rev_fifo.xco (2266, 2008-04-14)
SW_CODEC\src\codec_rev_fifo_to.vhd (2829, 2008-06-10)
SW_CODEC\src\codec_tx_fifo.vhd (5469, 2008-04-14)
SW_CODEC\src\codec_tx_fifo.xco (2254, 2008-04-14)
SW_CODEC\src\codec_tx_fifo_to.vhd (2628, 2009-06-28)
SW_CODEC\src\controller.vhd (7549, 2009-06-28)
SW_CODEC\src\credit.vhd (11947, 2009-06-28)
SW_CODEC\src\disconnect_checker.vhd (9114, 2009-06-28)
SW_CODEC\src\filter.vhd (3201, 2009-06-28)
SW_CODEC\src\ld_arith_reg.vhd (11255, 2008-06-10)
SW_CODEC\src\receiver.vhd (17247, 2009-06-28)
SW_CODEC\src\receive_sync.vhd (7252, 2009-06-28)
SW_CODEC\src\rx_clock_gen.vhd (5740, 2009-06-28)
SW_CODEC\src\rx_clock_sync.vhd (7431, 2009-06-28)
SW_CODEC\src\send_sync.vhd (13417, 2009-06-28)
SW_CODEC\src\sw_codec.vhd (28437, 2009-06-28)
SW_CODEC\src\sw_timer.vhd (6404, 2009-06-28)
SW_CODEC\src\sync_receiver.vhd (17000, 2009-06-28)
SW_CODEC\src\transmitter.vhd (36736, 2009-06-28)
SW_CODEC\src\tx_clk_gen.vhd (8169, 2009-06-28)
SW_CODEC\src (0, 2009-06-28)
SW_CODEC\syn\ise\ise.ise (319056, 2009-06-28)
SW_CODEC\syn\ise\ise.ise_ISE_Backup (319128, 2009-06-28)
SW_CODEC\syn\ise\ise.ntrc_log (240, 2009-06-28)
SW_CODEC\syn\ise\sw_codec_prev_built.ngd (231240, 2009-06-28)
SW_CODEC\syn\ise\sw_codec_summary.html (7441, 2009-06-28)
SW_CODEC\syn\ise\templates\coregen.xml (567, 2009-06-28)
SW_CODEC\syn\ise\templates (0, 2009-06-28)
SW_CODEC\syn\ise\tmp (0, 2009-06-28)
SW_CODEC\syn\ise\_xmsgs (0, 2009-06-28)
SW_CODEC\syn\ise (0, 2009-06-28)
... ...

本软件只是和大家交流学习。仅供学习研究，严禁商用 联系方式spacewire@163.com QQ群：90374657 1.仿真 进入Modelsim目录 运行compiler.scr 再键入vsim testbench即可 2.综合 采用VirtexII系列芯片进行综合结果如下 Logic Utilization: Number of Slice Flip Flops: 194 out of 18,560 1% Number of 4 input LUTs: 354 out of 18,560 1% Logic Distribution: Number of occupied Slices: 248 out of 9,280 2% Number of Slices containing only related logic: 248 out of 248 100% Number of Slices containing unrelated logic: 0 out of 248 0% *See NOTES below for an explanation of the effects of unrelated logic Total Number 4 input LUTs: 359 out of 18,560 1% Number used as logic: 354 Number used as a route-thru: 1 Number used as Shift registers: 4

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