文件列表:

S3E_Ethernet\board_files (0, 2009-06-18)
S3E_Ethernet\board_files\ddr_sdram (0, 2009-06-18)
S3E_Ethernet\board_files\ddr_sdram\folder_details.txt (2949, 2007-09-13)
S3E_Ethernet\board_files\ddr_sdram\verilog (0, 2009-06-18)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25 (0, 2009-06-18)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design (0, 2009-06-18)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\datasheet.txt (1553, 2008-01-07)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\design_testing.txt (1755, 2008-01-08)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\par (0, 2009-06-18)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\par\create_ise.bat (82, 2008-01-05)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\par\icon_coregen.xco (1344, 2008-01-04)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\par\ila_coregen.xco (3877, 2008-01-06)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\par\ise_flow.bat (972, 2008-01-06)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\par\ise_run.txt (916, 2008-01-04)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\par\mem_interface_top.ut (486, 2008-01-04)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\par\set_ise_prop.txt (6809, 2008-01-09)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\par\vlog_bl2cl25.bit (283872, 2008-01-06)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\par\vlog_bl2cl25.ucf (42002, 2008-01-06)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\sim (0, 2009-06-18)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\sim\ddr_model.v (60085, 2008-01-04)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\sim\ddr_model_parameters.vh (32487, 2008-01-04)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\sim\glbl.v (3257, 2008-01-04)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\sim\sim.do (4892, 2008-01-06)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\sim\sim_tb_top.v (15753, 2008-01-06)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\synth (0, 2009-06-18)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\synth\mem_interface_top_synp.sdc (2601, 2008-01-04)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\synth\script_synp.tcl (2822, 2008-01-04)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\synth\vlog_bl2cl25.lso (6, 2008-01-04)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\synth\vlog_bl2cl25.prj (1698, 2008-01-05)
S3E_Ethernet\board_files\ddr_sdram\verilog\vlog_bl2cl25\example_design\vlog_bl2cl25.cpj (25773, 2008-01-09)
S3E_Ethernet\board_files\ddr_sdram\vhdl (0, 2009-06-18)
S3E_Ethernet\board_files\ddr_sdram\vhdl\vhdl_bl4cl2 (0, 2009-06-18)
S3E_Ethernet\board_files\ddr_sdram\vhdl\vhdl_bl4cl2\example_design (0, 2009-06-18)
S3E_Ethernet\board_files\ddr_sdram\vhdl\vhdl_bl4cl2\example_design\datasheet.txt (1548, 2008-01-06)
S3E_Ethernet\board_files\ddr_sdram\vhdl\vhdl_bl4cl2\example_design\design_testing.txt (1753, 2008-01-09)
S3E_Ethernet\board_files\ddr_sdram\vhdl\vhdl_bl4cl2\example_design\par (0, 2009-06-18)
S3E_Ethernet\board_files\ddr_sdram\vhdl\vhdl_bl4cl2\example_design\par\create_ise.bat (82, 2008-01-06)
S3E_Ethernet\board_files\ddr_sdram\vhdl\vhdl_bl4cl2\example_design\par\icon_coregen.xco (1341, 2008-01-04)
S3E_Ethernet\board_files\ddr_sdram\vhdl\vhdl_bl4cl2\example_design\par\ila_coregen.xco (3874, 2008-01-06)
... ...

1. Spartan-3E Starter Kit supports DDR SDRAM(Component) memory design for Spartan-3E FPGA xc3s500efg320. 2. Above mentioned design were generated at 133MHz clock frequency. 3. You should go through the readme files provided in the corresponding design folders before using the bit files for testing Spartan-3E Starter Kit. 4. All the designs use the 133MHz onboard clock source as the design clock source. 5. Users can also regenerate the bit files by running ise_flow.bat file provided in par folder. 6. Inorder to perform simulations for the corresponding designs, you should copy "sim.exe" file from simulation_executable folder into respective sim folders. For further information on how to simulate the design, refer to the "simulation_help.chm" help file in the sim folder. 7. Please contact support.xilinx.com for Spartan-3E Starter Kit details.

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