文件列表:

verilog-A_library\copyright.txt (608, 2006-09-07)
verilog-A_library\motor\motor.va (1436, 2006-09-07)
verilog-A_library\motor\tb_sine.sp (440, 2006-09-07)
verilog-A_library\motor\tb_step.sp (411, 2006-09-07)
verilog-A_library\motor (0, 2008-12-24)
verilog-A_library\adc4a\adc4a.va (1329, 2006-09-07)
verilog-A_library\adc4a\adc_sub.sp (366, 2006-09-07)
verilog-A_library\adc4a (0, 2008-12-24)
verilog-A_library\laplace2\laplace2.va (1357, 2006-09-07)
verilog-A_library\laplace2\testFilter.sp (749, 2006-09-07)
verilog-A_library\laplace2 (0, 2008-12-24)
verilog-A_library\noiseTable\noiseTable.va (2169, 2006-09-07)
verilog-A_library\noiseTable\test_noiseTable.sp (589, 2006-09-07)
verilog-A_library\noiseTable (0, 2008-12-24)
verilog-A_library\noisy_resistor\noisy_resistor.va (840, 2006-09-07)
verilog-A_library\noisy_resistor\test.sp (218, 2006-09-07)
verilog-A_library\noisy_resistor (0, 2008-12-24)
verilog-A_library\diode\diode.va (893, 2006-09-07)
verilog-A_library\diode\resistor.va (758, 2006-09-07)
verilog-A_library\diode\test_diode.sp (646, 2006-09-07)
verilog-A_library\diode\top_diode.va (798, 2006-09-07)
verilog-A_library\diode (0, 2008-12-24)
verilog-A_library\parallelRLC\parallelRLC.va (1004, 2006-09-07)
verilog-A_library\parallelRLC\test_parallelRLC.sp (600, 2006-09-07)
verilog-A_library\parallelRLC (0, 2008-12-24)
verilog-A_library\ground\ground.va (881, 2006-09-07)
verilog-A_library\ground\resistor.va (801, 2006-09-07)
verilog-A_library\ground\test_ground.sp (205, 2006-09-07)
verilog-A_library\ground (0, 2008-12-24)
verilog-A_library\period\test_period.sp (399, 2006-09-07)
verilog-A_library\period\sine.va (983, 2006-09-07)
verilog-A_library\period\period.va (1133, 2006-09-07)
... ...

Test case ---------- In this test case an 8 bit verilog-a DAC(digital to analog converter) is driven by an ADC(Analog to digital converter). Input files: ----------- adc8.va --> Verilog-a ADC module. The input of this module is driven by a sinusoidal signal with a frequency of 1khz and its digital output is used to drive the DAC module. dacN.va --> Verilog-a DAC module. This file has been taken from the LRM manual and did following modifications to make it run using 2005.09 HSPICE. * Added `include "disciplines.vams" in to the module * Replaced the variable "width" with 8, since HSPICE doesn't support array bounds with a variable. test_dacN.sp --> Spice netlist which gives input vector/clock for ADC/DAC module. Expected results: ----------------- The input is a sinusoidal signal with a frequency of 1k and an amplitude of 2.5v with an offset of 2.5v. The same input signal can be seen at the output of the DAC module. How to run the test case -------------------------- hspice test_dacN.sp > test_dacN.lis version : 2005.09

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