viterbi
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：80KB
下载次数：30
上传日期：2009-07-04 11:20:38
上 传 者：
DM518
说明： Viterbi verilog generator
文件列表:
viterbi\acs2_mod.htm (1652, 2008-08-30)
viterbi\acs2.mod (1332, 2008-08-30)
viterbi\morpheus.tar.gz (34132, 2008-08-30)
viterbi\morpheus release\c\makefile (67, 2004-08-18)
viterbi\morpheus release\c (0, 2008-12-24)
viterbi\morpheus release\data\code (2688, 2004-04-26)
viterbi\morpheus release\data\source (442, 2004-04-26)
viterbi\morpheus release\data (0, 2008-12-24)
viterbi\morpheus release\module (0, 2008-12-24)
viterbi\morpheus release\perl\vit2cpp.pl (6497, 2004-09-01)
viterbi\morpheus release\perl\vit2.pl (4662, 2004-09-01)
viterbi\morpheus release\perl\virtual_mem.pl (3478, 2004-09-01)
viterbi\morpheus release\perl\utility.pl (5832, 2004-09-01)
viterbi\morpheus release\perl\trabacknew2.pl (9241, 2004-09-01)
viterbi\morpheus release\perl\testbench0.pl (5163, 2004-09-01)
viterbi\morpheus release\perl\smu0.pl (4672, 2004-09-01)
viterbi\morpheus release\perl\pe0.pl (4181, 2004-09-01)
viterbi\morpheus release\perl\Oraclet.pl (69305, 2004-09-01)
viterbi\morpheus release\perl\Oracle.pl.bak (4294, 2004-09-01)
viterbi\morpheus release\perl\morphsGUI.pl (7052, 2004-09-01)
viterbi\morpheus release\perl\morphs.pl (28712, 2004-09-01)
viterbi\morpheus release\perl\glb_def.pl (2347, 2004-09-01)
viterbi\morpheus release\perl\filo.pl (5681, 2004-09-01)
viterbi\morpheus release\perl\encode8.pl (3333, 2004-09-01)
viterbi\morpheus release\perl\ctrl.pl (7027, 2004-09-01)
viterbi\morpheus release\perl\decoder0.pl (4288, 2004-09-01)
viterbi\morpheus release\perl\Oracle.pl (4294, 2004-09-01)
viterbi\morpheus release\perl (0, 2008-12-24)
viterbi\morpheus release (0, 2008-12-24)
viterbi (0, 2008-12-24)
Run the following command to generate Verilog HDL codes in GUI:
$> perl perl/morphsGUI.pl
You need the perltk lib to run the GUI version, or you can run the command version:
$> perl perl/Oracle.pl
All Verilog HDL codes are put into "module" directory. An encoder written in C is generated under "c" directory for verification.
The file "source" in the "data" directory contains the binary vectors for test. In order to generate the encode data, you need to type this command:
$> c/encode8 < data/source > data/code
Then the encode data is prepared for simulation. And you can verify these Verilog HDL codes with any favorite simulator.
Good Luck!
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