example1
所属分类：嵌入式/单片机/硬件编程
开发工具：VHDL
文件大小：23KB
下载次数：2
上传日期：2009-07-05 10:29:54
上 传 者：
zzl_idea
说明： 实现一个将时钟信号CLK十分频的功能，可以通过波形仿真来看效果。
(The realization of a clock signal CLK is the frequency of the function, you can look at the effect of waveform simulation.)
文件列表:
example1\div.asm.rpt (6462, 2007-10-19)
example1\div.done (26, 2007-10-19)
example1\div.fit.rpt (43882, 2007-10-19)
example1\div.fit.smsg (334, 2007-10-19)
example1\div.fit.summary (352, 2007-10-19)
example1\div.flow.rpt (3873, 2007-10-19)
example1\div.map.rpt (17239, 2007-10-19)
example1\div.map.summary (281, 2007-10-19)
example1\div.pin (14717, 2007-10-19)
example1\div.pof (7855, 2007-10-19)
example1\div.qpf (903, 2007-09-04)
example1\div.qsf (1613, 2007-09-04)
example1\div.qws (1102, 2007-10-19)
example1\div.sim.rpt (9030, 2007-10-19)
example1\div.tan.rpt (15575, 2007-10-19)
example1\div.tan.summary (975, 2007-10-19)
example1\div.vhd (887, 2007-10-19)
example1\div.vwf (1950, 2007-09-04)
example1\db (0, 2009-07-05)
example1 (0, 2009-07-05)
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