VGA(FPGA)
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：4141KB
下载次数：123
上传日期：2009-07-11 17:12:13
上 传 者：
13475115012
说明： 基于FPGA的VGA工程文件以及相应的参考资料
(FPGA-based VGA engineering documents and the corresponding reference)
文件列表:
VGA(FPGA)\vga_ram_2\.sopc_builder\install.ptf (9761, 2006-09-11)
VGA(FPGA)\vga_ram_2\altpllpll_0.bsf (3943, 2006-08-30)
VGA(FPGA)\vga_ram_2\altpllpll_0.v (11552, 2006-08-30)
VGA(FPGA)\vga_ram_2\altpllpll_0_wave0.jpg (90327, 2006-08-30)
VGA(FPGA)\vga_ram_2\altpllpll_0_waveforms.html (636, 2006-08-30)
VGA(FPGA)\vga_ram_2\bht_ram.mif (2392, 2006-08-31)
VGA(FPGA)\vga_ram_2\Block1.bdf (33125, 2006-08-31)
VGA(FPGA)\vga_ram_2\button_pio.v (4251, 2006-08-31)
VGA(FPGA)\vga_ram_2\clock_0.v (26725, 2006-08-31)
VGA(FPGA)\vga_ram_2\clock_1.v (26725, 2006-08-30)
VGA(FPGA)\vga_ram_2\cpu_0.ocp (840, 2006-08-31)
VGA(FPGA)\vga_ram_2\cpu_0.v (379736, 2006-08-31)
VGA(FPGA)\vga_ram_2\cpu_0_jtag_debug_module.v (11362, 2006-08-31)
VGA(FPGA)\vga_ram_2\cpu_0_jtag_debug_module_wrapper.v (9543, 2006-08-31)
VGA(FPGA)\vga_ram_2\cpu_0_mult_cell.v (5218, 2006-08-31)
VGA(FPGA)\vga_ram_2\cpu_0_ociram_default_contents.mif (5878, 2006-08-31)
VGA(FPGA)\vga_ram_2\cpu_0_test_bench.v (37436, 2006-08-31)
VGA(FPGA)\vga_ram_2\db\add_sub_b7c.tdf (3362, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\add_sub_c7c.tdf (3533, 2006-08-30)
VGA(FPGA)\vga_ram_2\db\altsyncram_0kp.tdf (2571, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_1sq1.tdf (27075, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_5ms.tdf (24804, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_87r1.tdf (44206, 2006-08-30)
VGA(FPGA)\vga_ram_2\db\altsyncram_d1r1.tdf (26002, 2006-08-30)
VGA(FPGA)\vga_ram_2\db\altsyncram_f9c1.tdf (40548, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_ii51.tdf (42896, 2006-08-30)
VGA(FPGA)\vga_ram_2\db\altsyncram_ki51.tdf (42896, 2006-08-30)
VGA(FPGA)\vga_ram_2\db\altsyncram_kk61.tdf (2594, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_mi51.tdf (23648, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_n071.tdf (26452, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_prq1.tdf (22335, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_q1r1.tdf (44009, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_s202.tdf (45487, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_sjp.tdf (2587, 2006-08-30)
VGA(FPGA)\vga_ram_2\db\altsyncram_sr41.tdf (2615, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_toc1.tdf (12634, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_u2p1.tdf (44773, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_u5e1.tdf (6834, 2006-08-29)
VGA(FPGA)\vga_ram_2\db\altsyncram_ujp.tdf (2587, 2006-08-30)
VGA(FPGA)\vga_ram_2\db\altsyncram_um61.tdf (39600, 2006-08-29)
... ...
DE2_Top
-------
This design is a bare-bones design containing all the pin assignments available on the DE2 board. It also contains a Verilog module with all the input/output ports corresponding to each pin. This can be used as a starting point for designs on the board.
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