74HC161
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：1181KB
下载次数：154
上传日期：2009-07-14 10:14:52
上 传 者：
laosun_816
说明： 74ls161 基于verilog语言的实现 源程序在压缩包的hdl文件夹中
(74ls161 language based on the realization of verilog source package in compressed folder hdl)
文件列表:
74hc161.pdf (237284, 2009-06-08)
74hc161 (0, 2009-06-08)
74hc161\74hc161.prj (4329, 2009-06-05)
74hc161\component (0, 2009-06-08)
74hc161\constraint (0, 2009-06-08)
74hc161\coreconsole (0, 2009-06-08)
74hc161\designer (0, 2009-06-08)
74hc161\designer\impl1 (0, 2009-06-08)
74hc161\designer\impl1\count4.adb (53760, 2009-06-05)
74hc161\designer\impl1\count4.dtf (0, 2009-06-08)
74hc161\designer\impl1\count4.dtf\verify.log (233, 2009-06-05)
74hc161\designer\impl1\count4.ide_des (599, 2009-06-05)
74hc161\designer\impl1\count4.pdb (17408, 2009-06-05)
74hc161\designer\impl1\count4.pdb.depends (0, 2009-06-05)
74hc161\designer\impl1\count4.tcl (318, 2009-06-05)
74hc161\designer\impl1\count4_ba.sdf (21553, 2009-06-05)
74hc161\designer\impl1\count4_ba.v (7731, 2009-06-05)
74hc161\designer\impl1\count4_fp (0, 2009-06-08)
74hc161\designer\impl1\count4_fp\$$FlashPro_07294.L$$ (286, 2009-06-05)
74hc161\designer\impl1\count4_fp\count4.log (1059, 2009-06-05)
74hc161\designer\impl1\count4_fp\count4.pro (1583, 2009-06-05)
74hc161\designer\impl1\count4_fp\projectData (0, 2009-06-08)
74hc161\designer\impl1\count4_fp\projectData\count4.pdb (17408, 2009-06-05)
74hc161\designer\impl1\designer.log (370, 2009-06-05)
74hc161\designer\impl1\designer_gen_ba.log (462, 2009-06-05)
74hc161\designer\impl1\simulation (0, 2009-06-08)
74hc161\designer\impl1\testbench.ide_des (184, 2009-06-05)
74hc161\hdl (0, 2009-06-08)
74hc161\hdl\74hc161.v (2223, 2009-06-05)
74hc161\phy_synthesis (0, 2009-06-08)
74hc161\simulation (0, 2009-06-08)
74hc161\simulation\modelsim.ini (281, 2009-06-05)
74hc161\simulation\modelsim.ini.sav (260, 2009-06-05)
74hc161\simulation\modelsim.log (2523, 2009-06-05)
74hc161\simulation\presynth (0, 2009-06-08)
74hc161\simulation\presynth\count4 (0, 2009-06-08)
74hc161\simulation\presynth\count4\verilog.psm (8726, 2009-06-05)
74hc161\simulation\presynth\count4\_primary.dat (729, 2009-06-05)
74hc161\simulation\presynth\count4\_primary.dbs (1290, 2009-06-05)
74hc161\simulation\presynth\count4\_primary.vhd (470, 2009-06-05)
... ...
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