DDS
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：115KB
下载次数：846
上传日期：2009-08-03 13:19:50
上 传 者：
FJDSO
说明： 我们小组共了一个月做的DDS,程序核心用的是Verilog HDL,有仿真波形,输出正弦波,方波,及三角波,步进可调.频率范围1HZ--10MHZ
(Our group for a month to do a total of DDS, the procedure is used in the core of Verilog HDL, there are simulation waveform, the output sine wave, square wave and triangular wave, step adjustable. Frequency range 1HZ- 10MHZ)
文件列表:
DDS\creat.c (549, 2006-05-02)
DDS\512.mif (11119, 2006-05-02)
DDS\DDSFPGA.qpf (943, 2006-04-30)
DDS\DDSFPGA.qsf (2207, 2009-08-03)
DDS\romlookup.v (6091, 2006-05-02)
DDS\romlookup_bb.v (4831, 2006-05-02)
DDS\DDSFPGA.done (26, 2006-05-03)
DDS\DDSFPGA.bdf (16558, 2006-05-03)
DDS\DDSFPGA.qws (4465, 2009-08-03)
DDS\cmp_state.ini (2, 2006-05-03)
DDS\DDSFPGA.map.rpt (36962, 2006-05-03)
DDS\DDSFPGA.flow.rpt (3641, 2006-05-03)
DDS\DDSFPGA.map.summary (380, 2006-05-03)
DDS\squwave.bsf (2021, 2006-05-03)
DDS\Key.bsf (1921, 2006-05-03)
DDS\squwave.v.bak (348, 2006-05-01)
DDS\triawave.v.bak (401, 2006-05-01)
DDS\control.v.bak (312, 2006-05-01)
DDS\triawave.bsf (2026, 2006-05-03)
DDS\creat.exe (16523, 2006-05-02)
DDS\1024.mif (11120, 2006-05-02)
DDS\romlookup.bsf (2014, 2006-05-03)
DDS\control.bsf (2969, 2006-05-03)
DDS\datachoose.bsf (2772, 2006-05-03)
DDS\DDSFPGA.map.eqn (100146, 2006-05-03)
DDS\DDSFPGA.fit.eqn (145091, 2006-05-03)
DDS\DDSFPGA.pin (19503, 2006-05-03)
DDS\DDSFPGA.fit.rpt (91656, 2006-05-03)
DDS\DDSFPGA.fit.summary (442, 2006-05-03)
DDS\DDSFPGA.sof (74078, 2006-05-03)
DDS\DDSFPGA.pof (131258, 2006-05-03)
DDS\DDSFPGA.asm.rpt (7463, 2006-05-03)
DDS\DDSFPGA.tan.summary (1485, 2006-05-03)
DDS\DDSFPGA.tan.rpt (113844, 2006-05-03)
DDS\DDSFPGA.vwf (26837, 2006-05-03)
DDS\DDSFPGA.sim.rpt (4321, 2006-05-03)
DDS\datachoose.v (444, 2006-05-02)
DDS\clock_d2.v (211, 2006-05-02)
DDS\clock_d2.bsf (1617, 2006-05-03)
DDS\triawave.v (516, 2006-05-03)
... ...
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