文件列表:

Makefile (721, 2000-07-19)
VHDL (0, 2000-07-19)
www (0, 2000-07-19)
VHDL\fifo_test.vhd (7734, 2000-07-19)
VHDL\freefifo.vhd (51438, 2000-07-19)
VHDL\ramlib_quartus.vhd (6188, 2000-07-19)
VHDL\ramlib_sim.vhd (9090, 2000-07-19)
VHDL\ramlib_xil.vhd (42626, 2000-07-19)
VHDL\test_sim.vhd (5698, 2000-07-19)
VHDL\test_sim_dp2.vhd (9477, 2000-07-19)
VHDL\test_synth.vhd (5989, 2000-07-19)
VHDL\test_synth_dp2.vhd (9692, 2000-07-19)
www\_borders (0, 2000-07-19)
www\_derived (0, 2000-07-19)
www\_fpclass (0, 2000-07-19)
www\_overlay (0, 2000-07-19)
www\_private (0, 2000-07-19)
www\_themes (0, 2000-07-19)
www\_vti_cnf (0, 2000-07-19)
www\_vti_pvt (0, 2000-07-19)
www\download.html (2909, 2000-07-19)
www\fifo.h1.gif (1991, 2000-07-19)
www\fifo.h2.gif (1987, 2000-07-19)
www\fifo.html (22882, 2000-07-19)
www\images (0, 2000-07-19)
www\index.html (15295, 2000-07-19)
www\interf1.gif (2568, 2000-07-19)
www\interf2.gif (1969, 2000-07-19)
www\interf3.gif (2303, 2000-07-19)
www\ram_dp.html (7842, 2000-07-19)
www\ram_dp2.html (6137, 2000-07-19)
www\_borders\_vti_cnf (0, 2000-07-19)
www\_borders\bottom.htm (957, 2000-07-19)
www\_borders\_vti_cnf\bottom.htm (944, 2000-07-19)
www\_derived\_vti_cnf (0, 2000-07-19)
www\_derived\interface.htm_cmp_expeditn110_vbtn.gif (2904, 2000-07-19)
www\_derived\interface.htm_cmp_expeditn110_vbtn_a.gif (2419, 2000-07-19)
www\_derived\download.htm_cmp_expeditn110_vbtn.gif (2885, 2000-07-19)
www\_derived\download.htm_cmp_expeditn110_vbtn_a.gif (2417, 2000-07-19)
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---------------------------------------------------------------------------- ---------------------------------------------------------------------------- -- The Free IP Project -- VHDL Free-RAM Core -- (c) 1999-2000, The Free IP Project and David Kessner -- -- -- FREE IP GENERAL PUBLIC LICENSE -- TERMS AND CONDITIONS FOR USE, COPYING, DISTRIBUTION, AND MODIFICATION -- -- 1. You may copy and distribute verbatim copies of this core, as long -- as this file, and the other associated files, remain intact and -- unmodified. Modifications are outlined below. -- 2. You may use this core in any way, be it academic, commercial, or -- military. Modified or not. -- 3. Distribution of this core must be free of charge. Charging is -- allowed only for value added services. Value added services -- would include copying fees, modifications, customizations, and -- inclusion in other products. -- 4. If a modified source code is distributed, the original unmodified -- source code must also be included (or a link to the Free IP web -- site). In the modified source code there must be clear -- identification of the modified version. -- 5. Visit the Free IP web site for documentation and additional -- information. http://www.free-ip.com -- ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- This is version 0.6 (July 18, 2000) of the Free-RAM core Changes to v0.6: Added the ram_dp2 component. Changes to v0.5: Speed and size optimizations to fifo_rdcount/wrcount. Bug fix in fifo_rdcount. Changes to ramlib_xil.vhd for better unisim compatibility. Changes to v0.4: Added new FIFO's. ---------------------------------------------------------------------------- ---------------------------------------------------------------------------- This distribution contains the following files: readme.txt - What you're reading now. vhdl/ramlib_xil.vhd - VHDL code for use with Xilinx Foundation and/or FPGA Express. vhdl/ramlib_quartus.vhd - VHDL code for use with Altera Quartus (and possibly Max II+). vhdl/ramlib_sim.vhd - VHDL code for use with ModelTech ModelSIM. vhdl/freefifo.vhd - VHDL code for the FIFO's vhdl/test_sim.vhd - Testbench code for simulation of RAM's. vhdl/test_synth.vhd - Testbench for synthesis of RAM's. www/ - The HTML documentation ---------------------------------------------------------------------------- ----------------------------------------------------------------------------

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