IS61WV51216
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：3KB
下载次数：88
上传日期：2009-08-08 17:22:43
上 传 者：
fpga123
说明： iss simulation model for 512KX16 SRAM
文件列表:
IS61wv51216_testbench.v (1483, 2008-04-30)
IS61wv51216.v (7028, 2008-04-30)
*************************************************
* Verilog HDL Behavioral Modeling *
* 512K x 16 High Speed Async SRAM : IS61wv51216*
* Copyright(c) Integrated Silicon Solution, Inc.*
* All rights reserved. *
*************************************************
This is the 512K x 16 Async SRAM : IS61wv51216 Verilog HDL Behavioral Modeling model
under VERILOG-XL (CADENCE).
The version number of VERILOG-XL(CADENCE) is 2.6.19 .
File List :
IS61wv51216.v
IS61wv51216_testbench.v
IS61wv51216_readme.txt
Compiling method :
verilog
ex) verilog IS61wv51216.v IS61wv51216_testbench.v
Note ) For the different speed grade, customer need to change the each spec. times accordingly : IS61wv51216.v
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