motor_PWM_Verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：4913KB
下载次数：75
上传日期：2009-08-14 10:00:02
上 传 者：
redstars
说明： 直流电机的verilog hdl 代码，适合初学者参考
(DC motor verilog hdl code, suitable for beginners reference)
文件列表:
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\assert.log (200, 2007-09-25)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\constraint\pwm_top.pdc (825, 2007-10-15)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\constraint\top_sdc.sdc (509, 2007-09-25)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\control.adb (71680, 2007-09-25)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\control.ide_des (551, 2007-09-25)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\control.tcl (1279, 2007-09-25)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\designer.log (9191, 2007-10-15)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\designer_genhdl.log (7987, 2007-09-25)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\designer_gen_ba.log (437, 2007-09-25)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\stimulus\verilog.psm (20962, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\stimulus\_primary.dat (1695, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\stimulus\_primary.vhd (178, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\tb_clock_minmax\verilog.psm (22292, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\tb_clock_minmax\_primary.dat (2239, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\tb_clock_minmax\_primary.vhd (837, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\testbench\verilog.psm (1793, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\testbench\_primary.dat (295, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\testbench\_primary.vhd (78, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\top\verilog.psm (272066, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\top\_primary.dat (75285, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\top\_primary.vhd (211, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\simulation\postlayout\_info (1188, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\top.adb (462848, 2007-10-15)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\top.dtf\verify.log (233, 2007-10-15)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\top.ide_des (595, 2007-10-15)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\top.pdb (94720, 2007-10-15)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\top.pdb.depends (0, 2007-10-15)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\top.tcl (168, 2007-10-15)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\top_ba.sdf (289198, 2007-10-15)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\designer\impl1\top_ba.v (100728, 2007-10-15)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\hdl\hdlsynchk.tcl (111, 2007-12-11)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\hdl\PWM.v (2752, 2007-12-08)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\hdl\PWM_contr.v (3452, 2007-12-08)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\hdl\TOP.v (779, 2007-12-11)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\PWM.prj (7816, 2007-12-17)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\simulation\meminit.dat (2816, 2007-10-15)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\simulation\modelsim.ini (346, 2007-12-17)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\simulation\modelsim.ini.sav (344, 2007-12-17)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\simulation\modelsim.log (1287, 2007-09-27)
Core_PWM Verilog语言编写(可用于电机驱动)\PWM\Project\PWM\simulation\postsynth\@p@l@l_1\verilog.psm (7089, 2007-09-25)
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