cordicDDS
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：7KB
下载次数：170
上传日期：2009-08-15 23:28:44
上 传 者：
winwalk
说明： Cordic算法实现DDS的Verilog 源码,14位精度，非常实用的。
(DDS algorithm Cordic the Verilog source code, 14-bit accuracy, very practical.)
文件列表:
source\cordic.v (5450, 2007-11-13)
source\cordic.v.bak (5432, 2007-11-13)
source\cordic_dds.v (287, 2007-11-12)
source\cordic_elem.v (810, 2007-11-13)
source\cordic_elem.v.bak (810, 2007-11-13)
source\cordic_value.v (1498, 2007-11-13)
source\cordic_value.v.bak (1454, 2007-11-12)
source\msb_elem.v (251, 2007-11-12)
source\msb_elem.v.bak (250, 2007-11-12)
source\phase_acc.v (297, 2007-11-12)
source\phase_transform.v (429, 2007-11-13)
source\phase_transform.v.bak (591, 2007-11-13)
source\results.v.bak (1518, 2007-11-12)
source\sita_elem.v (515, 2007-11-12)
source\sita_table.v (584, 2007-11-12)
source\test_cordic.v (828, 2007-11-13)
source\xy_elem.v (873, 2007-11-13)
source\xy_elem.v.bak (807, 2007-11-12)
source (0, 2008-10-07)
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