说明：  基于硬件定点的完整的costas载波恢复环设计，FPGA设计可以用之参考。包括输入QPSK信号，16倍符号率采样，初始频差2.4KHz，以及低通滤波器的设计等待。最重要的是有本人的注释，易于上手。
(Hardware-based fixed-point of complete costas carrier recovery loop design, FPGA reference design can be used. Including input QPSK signal, 16 times the symbol rate sampling, the initial frequency difference 2.4KHz, and the design of low-pass filter to wait. The most important thing is to have my notes, easy to fly.)