VHDL100
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：6803KB
下载次数：13
上传日期：2009-08-24 18:09:32
上 传 者：
catcher03
说明： 这是一个包含100例精典VHDL语言例子的压缩包,里面有详细的程序说明.
(This is a VHDL language that contains examples of 100 cases of classics compressed packets, which have a detailed description of the procedures.)
文件列表:
VHDL100例\100vhdl例子\10_function\10_bit_to_int.vhd (896, 2003-02-17)
VHDL100例\100vhdl例子\11_wiredor\11_wiredor.vhd (858, 2003-02-17)
VHDL100例\100vhdl例子\12_convert\12_convert.vhd (695, 2003-02-17)
VHDL100例\100vhdl例子\13_SHL\13_SHL.VHD (421, 2003-02-17)
VHDL100例\100vhdl例子\14_MVL7_functions\14_MVL7_functions.vhd (13235, 2003-02-17)
VHDL100例\100vhdl例子\15_MUX41\15_MUX41.VHD (2055, 2003-02-17)
VHDL100例\100vhdl例子\15_MUX41\15_MVL7_functions.vhd (13237, 2003-02-17)
VHDL100例\100vhdl例子\15_MUX41\15_MVL7_syn_types.vhd (646, 2003-02-17)
VHDL100例\100vhdl例子\15_MUX41\15_test_vectors_mux41.vhd (5412, 2003-02-17)
VHDL100例\100vhdl例子\15_MUX41\15_TYPES.VHD (32169, 2003-02-17)
VHDL100例\100vhdl例子\16_MUX\16_multiple_mux.vhd (1813, 2003-02-17)
VHDL100例\100vhdl例子\16_MUX\16_MVL7_functions.vhd (13235, 2003-02-17)
VHDL100例\100vhdl例子\16_MUX\16_test_vectors.vhd (7843, 2003-02-17)
VHDL100例\100vhdl例子\16_MUX\16_TYPES.VHD (32169, 2003-02-17)
VHDL100例\100vhdl例子\16_MUX\TYPES.VHD (32169, 2003-02-17)
VHDL100例\100vhdl例子\17_parity\17_parity.vhd (2156, 2003-02-17)
VHDL100例\100vhdl例子\17_parity\17_test_bench.vhd (2056, 2003-02-17)
VHDL100例\100vhdl例子\18_LIB\18_tech_lib.vhd (49611, 2003-02-17)
VHDL100例\100vhdl例子\18_LIB\18_test_lib.vhd (1285, 2003-02-17)
VHDL100例\100vhdl例子\19_test_194\19_test_194.vhd (534, 2003-02-17)
VHDL100例\100vhdl例子\1_ADDER\1_ADDER\1_ADDER.exp (1139, 2003-02-17)
VHDL100例\100vhdl例子\1_ADDER\1_ADDER\files\L1.rpt (626, 2003-02-17)
VHDL100例\100vhdl例子\1_ADDER\1_ADDER\files\L2.rpt (626, 2003-02-17)
VHDL100例\100vhdl例子\1_ADDER\1_ADDER\files\L3.rpt (637, 2003-02-17)
VHDL100例\100vhdl例子\1_ADDER\1_ADDER\workdirs\aa\ADDER.sim (4815, 2003-02-17)
VHDL100例\100vhdl例子\1_ADDER\1_ADDER\workdirs\aa\ADDER.syn (512, 2003-02-17)
VHDL100例\100vhdl例子\1_ADDER\1_ADDER\workdirs\aa\Anal.info (28, 2003-02-17)
VHDL100例\100vhdl例子\1_ADDER\1_ADDER\workdirs\aa\Anal.out (238, 2003-02-17)
VHDL100例\100vhdl例子\1_ADDER\1_ADDER\workdirs\WORK\Anal.info (28, 2003-02-17)
VHDL100例\100vhdl例子\1_ADDER\1_ADDER\workdirs\WORK\Anal.out (227, 2003-02-17)
VHDL100例\100vhdl例子\1_ADDER\1_ADDER\workdirs\WORK\BIT_RTL_ADDER.sim (4954, 2003-02-17)
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