说明：  本例程属于独立实验，主要是让大家熟悉一下VHDL 语言基本语法，这是比较简单的 程序了。实现一个将时钟信号clk 十分频的功能，可以通过波形仿真来看效果。 波形仿真的过程可以参考视频“波形仿真.exe”文件，有比较详细的操作方法。其实 在例程的项目中已经包含了波形仿真文件，大家可以直接仿真，观察结果。
(This routine is an independent experiment is designed to allow you familiarize yourself with the basic syntax of VHDL language, which is relatively simple program. To achieve a clock signal clk is the frequency of the function, you can look at the waveform simulation results. Waveform simulation process can refer to video " wave simulation. Exe" file, there is a more detailed method of operation. In fact, routine project already contains a waveform simulation file, we can direct simulation, observe the results.)