modelsim
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：367KB
下载次数：18
上传日期：2009-08-27 13:14:41
上 传 者：
lihua38307308
说明： 用verilog编写的基于流水线结构的16阶滤波器的实现
(filter )
文件列表:
modelsim\222.BMP (416154, 2009-06-03)
modelsim\add.v (503, 2009-06-02)
modelsim\add.v.bak (515, 2009-06-02)
modelsim\afternoon.cr.mti (2085, 2009-06-07)
modelsim\afternoon.mpf (29659, 2009-06-07)
modelsim\clk.v (451, 2009-06-02)
modelsim\clk.v.bak (451, 2009-06-02)
modelsim\inputshift.v (1456, 2009-06-02)
modelsim\lut.v (1927, 2009-06-02)
modelsim\mul.v (1004, 2009-06-02)
modelsim\mul.v.bak (664, 2009-06-02)
modelsim\out.v (294, 2009-06-02)
modelsim\out.v.bak (294, 2009-06-02)
modelsim\outputadd.v (545, 2009-06-02)
modelsim\outputadd.v.bak (484, 2009-06-02)
modelsim\outputshift.v (1173, 2009-06-02)
modelsim\outputshift.v.bak (1173, 2009-06-02)
modelsim\ram.patt (328, 2009-06-03)
modelsim\ramh.patt (174, 2009-06-03)
modelsim\Snap1.bmp (674294, 2009-06-03)
modelsim\test_top.v (837, 2009-06-02)
modelsim\test_top.v.bak (839, 2009-06-02)
modelsim\top.bmp (504926, 2009-06-03)
modelsim\top.v (3512, 2009-06-02)
modelsim\top.v.bak (3512, 2009-06-02)
modelsim\transcript (480, 2009-06-11)
modelsim\vsim.wlf (40960, 2009-06-07)
modelsim\ISE\ise\add.v (503, 2009-06-02)
modelsim\ISE\ise\clk.spl (84, 2009-06-03)
modelsim\ISE\ise\clk.sym (649, 2009-06-03)
modelsim\ISE\ise\clk.v (451, 2009-06-02)
modelsim\ISE\ise\clk.vhi (553, 2009-06-03)
modelsim\ISE\ise\inputshift.v (1456, 2009-06-02)
modelsim\ISE\ise\ise.ise (248995, 2009-06-10)
modelsim\ISE\ise\ise.ise_ISE_Backup (248995, 2009-06-10)
modelsim\ISE\ise\ise.ntrc_log (55, 2009-06-03)
modelsim\ISE\ise\lut.v (1927, 2009-06-02)
modelsim\ISE\ise\mul.v (1004, 2009-06-02)
modelsim\ISE\ise\out.v (294, 2009-06-02)
modelsim\ISE\ise\outputadd.v (545, 2009-06-02)
... ...
近期下载者：
相关文件：
收藏者：