reload_fir
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：16335KB
下载次数：114
上传日期：2009-08-29 10:40:27
上 传 者：
gh1232008
说明： 这是我在Xilinx公司的FPGA上实现的FIR滤波器，调用的内部核，其特色是可以用较少的资源实现该功能，而且可以实现参数重载，即从外部MCU设置FIR滤波器的参数
(This is my Xilinx FPGA to achieve the FIR filter, called internal audit, its characteristics can be achieved with fewer resources to this function, and the overload parameters can be achieved, that is, from an external MCU to set the parameters of FIR Filter)
文件列表:
core_resources.txt (21, 2009-08-25)
dds.asy (513, 2009-08-03)
dds.ngc (68362, 2009-08-03)
dds.sym (813, 2009-08-03)
dds.v (49416, 2009-08-03)
dds.veo (3021, 2009-08-03)
dds.vhd (46527, 2009-08-03)
dds.vho (3473, 2009-08-03)
dds.xco (1701, 2009-08-03)
dds_cs.cdc (2677, 2009-08-03)
dds_flist.txt (164, 2009-08-03)
dds_icon.asy (187, 2009-08-03)
dds_icon.ncf (425, 2009-08-03)
dds_icon.v (41949, 2009-08-03)
dds_icon.veo (1080, 2009-08-03)
dds_icon.vhd (46859, 2009-08-03)
dds_icon.vho (1309, 2009-08-03)
dds_icon.xco (1307, 2009-08-03)
dds_icon_flist.txt (188, 2009-08-03)
dds_icon_xmdf.tcl (3017, 2009-08-03)
dds_SINCOS_TABLE_TRIG_ROM.mif (14336, 2009-08-03)
dds_tbw.ant (3618, 2009-08-26)
dds_tbw.fdo (514, 2009-08-26)
dds_tbw.jhd (46, 2009-08-26)
dds_tbw.tbw (951, 2009-08-26)
dds_tbw.tfw (1371, 2009-08-26)
dds_tbw.udo (110, 2009-08-03)
dds_tbw.xwv (21436, 2009-08-26)
dds_tbw.xwv_bak (21436, 2009-08-26)
dds_tbw_beh.prj (175, 2009-08-24)
dds_tbw_bencher.prj (170, 2009-08-26)
dds_tbw_isim_beh.exe (17229, 2009-08-24)
dds_tbw_isim_beh.wfs (740, 2009-08-24)
dds_tbw_wave.fdo (147, 2009-08-03)
dds_vio.asy (268, 2009-08-03)
dds_vio.cdc (801, 2009-08-03)
dds_vio.ncf (95, 2009-08-03)
dds_vio.v (59680, 2009-08-03)
... ...
The following files were generated for 'dds' in directory
D:\NODeleting\ISE\TEST:
dds.asy:
Graphical symbol information file. Used by the ISE tools and some
third party tools to create a symbol representing the core.
dds.ngc:
Binary Xilinx implementation netlist file containing the information
required to implement the module in a Xilinx (R) FPGA.
dds.sym:
Please see the core data sheet.
dds.v:
Verilog wrapper file provided to support functional simulation.
This file contains simulation model customization data that is
passed to a parameterized simulation model for the core.
dds.veo:
VEO template file containing code that can be used as a model for
instantiating a CORE Generator module in a Verilog design.
dds.vhd:
VHDL wrapper file provided to support functional simulation. This
file contains simulation model customization data that is passed to
a parameterized simulation model for the core.
dds.vho:
VHO template file containing code that can be used as a model for
instantiating a CORE Generator module in a VHDL design.
dds.xco:
CORE Generator input file containing the parameters used to
regenerate a core.
dds_SINCOS_TABLE_TRIG_ROM.mif:
Memory Initialization File which is automatically generated by the
CORE Generator System for some modules when a simulation flow is
specified. A MIF data file is used to support HDL functional
simulation of modules which use arrays of values.
dds_flist.txt:
Text file listing all of the output files produced when a customized
core was generated in the CORE Generator.
dds_readme.txt:
Text file indicating the files generated and how they are used.
dds_xmdf.tcl:
ISE Project Navigator interface file. ISE uses this file to determine
how the files output by CORE Generator for the core can be integrated
into your ISE project.
Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.
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