VerilogHDL
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：19479KB
下载次数：36
上传日期：2009-09-01 20:04:51
上 传 者：
andysanshaoye
说明： Verilog HDL 程序设计实例详解
Verilog HDL 程序设计实例详解
(Verilog HDL programming example explanation example explanation of Verilog HDL programming)
文件列表:
Chapter-1\adder\adder.cr.mti (512, 2007-08-18)
Chapter-1\adder\adder.mpf (16771, 2007-08-18)
Chapter-1\adder\adder.v (201, 2007-08-03)
Chapter-1\adder\adder_testbench.do (870, 2007-08-15)
Chapter-1\adder\adder_testbench.v (549, 2007-08-03)
Chapter-1\adder\chart\ͼ1-3.bmp (586974, 2007-08-18)
Chapter-1\adder\chart\ͼ1-4.bmp (807726, 2007-08-18)
Chapter-1\adder\chart\ͼ1-5.bmp (630774, 2007-08-18)
Chapter-1\adder\chart\ͼ1-6.bmp (763926, 2007-08-18)
Chapter-1\adder\chart\ͼ1-7.bmp (676326, 2007-08-18)
Chapter-1\adder\chart\ͼ1-8.bmp (353958, 2007-08-18)
Chapter-1\adder\transcript (389, 2007-12-17)
Chapter-1\adder\vsim.wlf (32768, 2007-08-15)
Chapter-1\adder\work\adder\transcript (389, 2007-12-17)
Chapter-1\adder\work\adder\verilog.txt.asm (2424, 2007-08-18)
Chapter-1\adder\work\adder\_primary.dat (162, 2007-08-18)
Chapter-1\adder\work\adder\_primary.vhd (258, 2007-08-18)
Chapter-1\adder\work\adder_testbench\verilog.asm (6855, 2007-08-18)
Chapter-1\adder\work\adder_testbench\_primary.dat (556, 2007-08-18)
Chapter-1\adder\work\adder_testbench\_primary.vhd (90, 2007-08-18)
Chapter-1\adder\work\_info (340, 2007-08-18)
Chapter-2\2.1\adder (158210, 2007-08-18)
Chapter-2\2.1\adder.cr.mti (504, 2007-08-18)
Chapter-2\2.1\adder.mpf (16767, 2007-08-18)
Chapter-2\2.1\adder.v (201, 2007-08-03)
Chapter-2\2.1\adder_testbench.v (549, 2007-08-03)
Chapter-2\2.1\chart\ͼ2-2.bmp (304206, 2007-12-24)
Chapter-2\2.1\chart\表2-1.bmp (114966, 2007-08-18)
Chapter-2\2.1\transcript (2331, 2007-08-18)
Chapter-2\2.1\vsim.wlf (32768, 2007-08-18)
Chapter-2\2.1\wave\adder.bmp (303434, 2007-08-18)
Chapter-2\2.1\wave\adder_testbench.bmp (321726, 2007-08-18)
Chapter-2\2.1\work\adder\verilog.asm (2424, 2007-08-18)
Chapter-2\2.1\work\adder\_primary.dat (162, 2007-08-18)
Chapter-2\2.1\work\adder\_primary.vhd (258, 2007-08-18)
Chapter-2\2.1\work\adder_testbench\verilog.asm (6855, 2007-08-18)
Chapter-2\2.1\work\adder_testbench\_primary.dat (556, 2007-08-18)
Chapter-2\2.1\work\adder_testbench\_primary.vhd (90, 2007-08-18)
Chapter-2\2.1\work\_info (377, 2007-08-18)
Chapter-2\2.2\chart\ͼ2-4.bmp (323434, 2007-12-24)
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