文件列表:

100M_mac\eth_speci.pdf (156727, 2008-10-16)
100M_mac\eth_design_document.pdf (115256, 2008-10-16)
100M_mac\ethernet_datasheet_OC_head.pdf (20169, 2008-10-16)
100M_mac\ethernet.tar.gz (936521, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\log\CVS\Repository (25, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\log\CVS\Entries (45, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\log\CVS\Root (13, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\log\dir_keeper (0, 2003-07-18)
100M_mac\ethernet\ethernet\sim\rtl_sim\out\CVS\Repository (25, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\out\CVS\Entries (45, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\out\CVS\Root (13, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\out\dir_keeper (0, 2003-07-18)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\log\dir.keeper (0, 2002-09-18)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\log\CVS\Repository (38, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\log\CVS\Entries (48, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\log\CVS\Root (13, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\out\dir.keeper (0, 2002-09-18)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\out\CVS\Repository (38, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\out\CVS\Entries (48, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\out\CVS\Root (13, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\bin\eth_wave.do (10799, 2002-10-18)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\bin\do.do (2951, 2002-09-18)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\bin\work\dir.keeper (0, 2002-09-18)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\bin\work\_info (53, 2002-09-18)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\bin\work\CVS\Repository (43, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\bin\work\CVS\Entries (86, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\bin\work\CVS\Root (13, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\bin\ethernet.mpf (21268, 2002-09-18)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\bin\CVS\Repository (38, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\bin\CVS\Entries (179, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\bin\CVS\Root (13, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\bin\vlog.opt (66, 2002-09-18)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\CVS\Repository (34, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\CVS\Entries (40, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\CVS\Root (13, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\run\dir.keeper (0, 2002-09-18)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\run\CVS\Repository (38, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\run\CVS\Entries (90, 2008-10-16)
100M_mac\ethernet\ethernet\sim\rtl_sim\modelsim_sim\run\CVS\Root (13, 2008-10-16)
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////////////////////////////////////////////////////////////////////// //// //// //// README.txt //// //// //// //// This file is part of the Ethernet IP core project //// //// http://www.opencores.org/projects/ethmac/ //// //// //// //// Author(s): //// //// - Igor Mohor (igorM@opencores.org) //// //// //// //// //// ////////////////////////////////////////////////////////////////////// //// //// //// Copyright (C) 2001, 2002 Authors //// //// //// //// This source file may be used and distributed without //// //// restriction provided that this copyright statement is not //// //// removed from the file and that any derivative work contains //// //// the original copyright notice and the associated disclaimer. //// //// //// //// This source file is free software; you can redistribute it //// //// and/or modify it under the terms of the GNU Lesser General //// //// Public License as published by the Free Software Foundation; //// //// either version 2.1 of the License, or (at your option) any //// //// later version. //// //// //// //// This source is distributed in the hope that it will be //// //// useful, but WITHOUT ANY WARRANTY; without even the implied //// //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //// //// PURPOSE. See the GNU Lesser General Public License for more //// //// details. //// //// //// //// You should have received a copy of the GNU Lesser General //// //// Public License along with this source; if not, download it //// //// from http://www.opencores.org/lgpl.shtml //// //// //// ////////////////////////////////////////////////////////////////////// // // CVS Revision History // // $Log: README.txt,v $ // Revision 1.1 2002/09/18 16:50:08 mohor // Several information added to the file. // // // // RUNNING the simulation/Testbench in ModelSIM: Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf Run the macro do.do (write "do do.do" in the command window). Simulation will be automatically started. Logs are stored in the /log directory. tb_ethernet test is performed. RUNNING the simulation/Testbench in Ncsim: Go to the ethernet\sim\rtl_sim\ncsim_sim\run directory. Run the run_eth_sim_regr.scr script. Simulation is automatically started. Logs are stored in the /log directory. Before running the script for another time, run the clean script that deletes files from previous runs. tb_ethernet test is performed. Why are eth_cop.v, eth_host.v, eth_memory, tb_cop.v and tb_ethernet_with_cop.v files used for? Although the testbench does not include the traffic coprocessor, the coprocessor is part of the ethernet environment. eth_cop multiplexes two wishbone interface between 4 modules: - First wishbone master interface is connected to the HOST (eth_host) - Second wishbone master interface is connected to the Ethernet Core (for accessing data in the memory (eth_memory)). - First wishbone slave interface is connected to the Ethernet Core (for accessing registers and buffer descriptors). - Second wishbone slave interface is connected to the memory (eth_memory) so host can write data to the memory (or read data from the memory. tb_cop.c is a testbench just for the traffic coprocessor (eth_cop). tb_ethernet_with_cop.v is a simple testbench where all above mentioned modules are connected into a single environment. Few packets are transmitted and received. The "main" testbench is tb_ethernet.v file. It performs several tests (eth_cop is not part of the simulation environment).

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