statemachine
所属分类：VHDL/FPGA/Verilog
开发工具：Visual C++
文件大小：4195KB
下载次数：12
上传日期：2009-09-21 19:23:14
上 传 者：
cheng066
说明： 采用systemc语言设计了一个状态机，主要包括两个进程，仿真结果表明状态机可以正常工作
(Systemc language designed using a state machine, mainly consists of two processes, the simulation results show that the state machine can work properly)
文件列表:
statemachine\Debug\main.obj (402668, 2009-05-09)
statemachine\Debug\statemachine.exe (1785927, 2009-05-09)
statemachine\Debug\statemachine.ilk (2451164, 2009-05-09)
statemachine\Debug\statemachine.pch (13352696, 2009-05-09)
statemachine\Debug\statemachine.pdb (3073024, 2009-05-09)
statemachine\Debug\vc60.idb (386048, 2009-05-09)
statemachine\Debug\vc60.pdb (438272, 2009-05-09)
statemachine\main.cpp (625, 2009-05-09)
statemachine\modelsim\statemachine\state.cr.mti (2, 2009-05-13)
statemachine\modelsim\statemachine\state.mpf (20227, 2009-05-09)
statemachine\modelsim\statemachine\state.vcd (1534, 2009-05-09)
statemachine\modelsim\statemachine\state.wlf (16384, 2009-05-09)
statemachine\modelsim\statemachine\transcript (447, 2009-05-09)
statemachine\modelsim\statemachine\work\_info (66, 2009-05-08)
statemachine\state.cpp (879, 2009-04-30)
statemachine\state.h (1550, 2009-05-09)
statemachine\state.vcd (1534, 2009-05-09)
statemachine\statemachine.dsp (4608, 2009-05-08)
statemachine\statemachine.dsw (547, 2009-05-08)
statemachine\statemachine.ncb (50176, 2009-05-09)
statemachine\statemachine.opt (48640, 2009-05-09)
statemachine\statemachine.plg (1394, 2009-05-09)
statemachine\tb.h (734, 2009-05-09)
statemachine\modelsim\statemachine\work (0, 2009-09-21)
statemachine\modelsim\statemachine (0, 2009-09-21)
statemachine\Debug (0, 2009-05-14)
statemachine\modelsim (0, 2009-09-21)
statemachine (0, 2009-09-21)
近期下载者：
相关文件：
收藏者：