baseband_verilog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：26KB
下载次数：292
上传日期：2009-10-08 10:19:34
上 传 者：
uestcgaopeng
说明： verilog实现的基带信号编码，整个系统分为六个模块，分别为：时钟模块,待发射模块,卷积模块,扩频模块,极性变换和内插模块,成型滤波器
(verilog implementation baseband signal coding, the entire system is divided into six modules, namely: the clock module, to be launched modules, convolution module, spread spectrum modules, polarity transform and interpolation modules, forming filter)
文件列表:
baseband_verilog\accumulator.v (2573, 2007-01-02)
baseband_verilog\carrier_mixer.v (2162, 2007-01-02)
baseband_verilog\carrier_nco.v (6527, 2007-01-02)
baseband_verilog\code_gen2.v (8129, 2007-01-02)
baseband_verilog\code_nco.v (3769, 2007-01-02)
baseband_verilog\epoch_counter.v (3492, 2007-01-02)
baseband_verilog\gps_baseband.v (44299, 2007-03-02)
baseband_verilog\lgpl.txt (26436, 2007-01-02)
baseband_verilog\time_base.v (4616, 2007-08-20)
baseband_verilog\tracking_channel.v (6060, 2007-01-02)
baseband_verilog (0, 2008-07-01)
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