文件列表:

rs422\transform_image\blk_mem_gen_ds512.pdf (2107313, 2009-04-30)
rs422\transform_image\blk_mem_gen_release_notes.txt (4492, 2009-04-30)
rs422\transform_image\fifo.mif (72, 2009-04-30)
rs422\transform_image\fifo.ngc (14656, 2009-04-30)
rs422\transform_image\fifo.vhd (5066, 2009-04-30)
rs422\transform_image\fifo.vho (3491, 2009-04-30)
rs422\transform_image\fifo.xco (2142, 2009-04-30)
rs422\transform_image\fifo_blk_mem_gen_v2_4_xst_1_vhdl.prj (2222, 2009-04-30)
rs422\transform_image\fifo_flist.txt (154, 2009-04-30)
rs422\transform_image\fifo_xmdf.tcl (2656, 2009-04-30)
rs422\transform_image\image_data\.lso (6, 2009-05-04)
rs422\transform_image\image_data\blk_mem_gen_ds512.pdf (2107313, 2009-06-03)
rs422\transform_image\image_data\blk_mem_gen_release_notes.txt (4492, 2009-06-03)
rs422\transform_image\image_data\coregen_lock (0, 2009-06-03)
rs422\transform_image\image_data\fifo.mif (144, 2009-06-03)
rs422\transform_image\image_data\fifo.ngc (14608, 2009-06-03)
rs422\transform_image\image_data\fifo.vhd (5066, 2009-06-03)
rs422\transform_image\image_data\fifo.vho (3491, 2009-06-03)
rs422\transform_image\image_data\fifo.xco (2153, 2009-04-30)
rs422\transform_image\image_data\fifo_blk_mem_gen_v2_4_xst_1.lso (18, 2009-06-03)
rs422\transform_image\image_data\fifo_blk_mem_gen_v2_4_xst_1_vhdl.prj (2420, 2009-06-03)
rs422\transform_image\image_data\fifo_flist.txt (154, 2009-06-03)
rs422\transform_image\image_data\fifo_xmdf.tcl (2656, 2009-06-03)
rs422\transform_image\image_data\fq_multiple.cmd_log (136, 2009-05-05)
rs422\transform_image\image_data\fq_multiple.lso (6, 2009-05-05)
rs422\transform_image\image_data\fq_multiple.ngc (3228, 2009-05-05)
rs422\transform_image\image_data\fq_multiple.ngr (2778, 2009-05-05)
rs422\transform_image\image_data\fq_multiple.prj (55, 2009-05-05)
rs422\transform_image\image_data\fq_multiple.stx (0, 2009-05-05)
rs422\transform_image\image_data\fq_multiple.syr (13202, 2009-05-05)
rs422\transform_image\image_data\fq_multiple.vhd (1401, 2009-05-03)
rs422\transform_image\image_data\fq_multiple.xst (1145, 2009-05-05)
rs422\transform_image\image_data\fq_multiple_summary.html (3354, 2009-06-03)
rs422\transform_image\image_data\fq_multiple_vhdl.prj (161, 2009-05-05)
rs422\transform_image\image_data\fq_ram.vhd (1535, 2009-04-30)
rs422\transform_image\image_data\image_data.ise (378877, 2009-06-03)
rs422\transform_image\image_data\image_data.ise_ISE_Backup (378877, 2009-06-03)
rs422\transform_image\image_data\image_data.ntrc_log (1540, 2009-05-04)
... ...

The following files were generated for 'fifo' in directory D:\Xilinx92i_exmple\rs422\transform_image\: fifo.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. fifo.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA. fifo.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. fifo.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. fifo.xco: CORE Generator input file containing the parameters used to regenerate a core. fifo_blk_mem_gen_v2_4_xst_1_vhdl.prj: Please see the core data sheet. fifo_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. fifo_readme.txt: Text file indicating the files generated and how they are used. fifo_xmdf.tcl: Please see the core data sheet. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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