ethernet
所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:825KB
下载次数:230
上传日期:2009-10-21 14:32:31
上 传 者:
mgwei
说明: 以太网MAC层IP核设计Veriolg代码,包括TESTBECH平台和设计文档
(Ethernet MAC layer IP core design Veriolg code, including TESTBECH platform and design documents)
文件列表:
ethernet\ethernet.companion (2368, 2006-06-14)
ethernet\rtl\verilog\BUGS (3335, 2006-06-14)
ethernet\rtl\verilog\eth_clockgen.v (5836, 2006-06-14)
ethernet\rtl\verilog\eth_cop.v (13755, 2006-06-14)
ethernet\rtl\verilog\eth_crc.v (7658, 2006-06-14)
ethernet\rtl\verilog\eth_defines.v (12282, 2006-06-14)
ethernet\rtl\verilog\eth_fifo.v (6099, 2006-06-14)
ethernet\rtl\verilog\eth_maccontrol.v (12372, 2006-06-14)
ethernet\rtl\verilog\eth_macstatus.v (12880, 2006-06-14)
ethernet\rtl\verilog\eth_miim.v (16705, 2006-06-14)
ethernet\rtl\verilog\eth_outputcontrol.v (6669, 2006-06-14)
ethernet\rtl\verilog\eth_random.v (6284, 2006-06-14)
ethernet\rtl\verilog\eth_receivecontrol.v (14753, 2006-06-14)
ethernet\rtl\verilog\eth_register.v (4968, 2006-06-14)
ethernet\rtl\verilog\eth_registers.v (28882, 2006-06-14)
ethernet\rtl\verilog\eth_rxaddrcheck.v (7629, 2006-06-14)
ethernet\rtl\verilog\eth_rxcounters.v (8823, 2006-06-14)
ethernet\rtl\verilog\eth_rxethmac.v (13707, 2006-06-14)
ethernet\rtl\verilog\eth_rxstatem.v (7863, 2006-06-14)
ethernet\rtl\verilog\eth_shiftreg.v (7097, 2006-06-14)
ethernet\rtl\verilog\eth_spram_256x32.v (6986, 2006-06-14)
ethernet\rtl\verilog\eth_top.v (35665, 2006-06-14)
ethernet\rtl\verilog\eth_transmitcontrol.v (11387, 2006-06-14)
ethernet\rtl\verilog\eth_txcounters.v (9270, 2006-06-14)
ethernet\rtl\verilog\eth_txethmac.v (18052, 2006-06-14)
ethernet\rtl\verilog\eth_txstatem.v (10800, 2006-06-14)
ethernet\rtl\verilog\eth_wishbone.v (72282, 2006-06-14)
ethernet\rtl\verilog\nLint.rc (4021, 2008-05-28)
ethernet\rtl\verilog\timescale.v (3371, 2006-06-14)
ethernet\rtl\verilog\TODO (4055, 2006-06-14)
ethernet\rtl\verilog (0, 2009-02-12)
ethernet\rtl (0, 2009-02-12)
ethernet\doc\ethernet_datasheet_OC_head.pdf (20169, 2006-06-14)
ethernet\doc\ethernet_product_brief_OC_head.pdf (19905, 2006-06-14)
ethernet\doc\eth_design_document.pdf (162784, 2006-06-14)
ethernet\doc\eth_speci.pdf (254051, 2006-06-14)
ethernet\doc\src\ethernet_datasheet_OC_head.doc (174592, 2006-06-14)
ethernet\doc\src\ethernet_product_brief_OC_head.doc (157184, 2006-06-14)
ethernet\doc\src\eth_design_document.doc (426496, 2006-06-14)
... ...
//////////////////////////////////////////////////////////////////////
//// ////
//// README.txt ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor (igorM@opencores.org) ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001, 2002 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: README.txt,v $
// Revision 1.1 2006/06/14 08:04:04 tom
// Initial version for new CVS tree
//
// Revision 1.1 2005/08/18 09:45:17 tom
// Initial version for new CVS tree
//
// Revision 1.1 2004/08/26 12:25:31 tom
// Initial version for new CVS tree
//
// Revision 1.1 2003/07/10 10:20:32 willem
// Initial version
//
// Revision 1.1 2002/09/18 16:50:08 mohor
// Several information added to the file.
//
//
//
//
RUNNING the simulation/Testbench in ModelSIM:
Open ModelSIM project: ethernet/sim/rtl_sim/modelsim_sim/bin/ethernet.mpf
Run the macro do.do (write "do do.do" in the command window).
Simulation will be automatically started. Logs are stored in the /log
directory. tb_ethernet test is performed.
RUNNING the simulation/Testbench in Ncsim:
Go to the ethernet\sim\rtl_sim\ncsim_sim\run directory. Run the
run_eth_sim_regr.scr script. Simulation is automatically started. Logs are
stored in the /log directory. Before running the script for another time,
run the clean script that deletes files from previous runs. tb_ethernet test
is performed.
Why are eth_cop.v, eth_host.v, eth_memory, tb_cop.v and tb_ethernet_with_cop.v
files used for?
Although the testbench does not include the traffic coprocessor, the
coprocessor is part of the ethernet environment. eth_cop multiplexes
two wishbone interface between 4 modules:
- First wishbone master interface is connected to the HOST (eth_host)
- Second wishbone master interface is connected to the Ethernet Core (for
accessing data in the memory (eth_memory)).
- First wishbone slave interface is connected to the Ethernet Core (for
accessing registers and buffer descriptors).
- Second wishbone slave interface is connected to the memory (eth_memory)
so host can write data to the memory (or read data from the memory.
tb_cop.c is a testbench just for the traffic coprocessor (eth_cop).
tb_ethernet_with_cop.v is a simple testbench where all above mentioned
modules are connected into a single environment. Few packets are transmitted
and received. The "main" testbench is tb_ethernet.v file. It performs several
tests (eth_cop is not part of the simulation environment).
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