文件列表:

开发板实验例程\labdocs\01_tool_flow_demo_9.doc (2196480, 2007-01-29)
开发板实验例程\labdocs\02_arwz_pace_demo_9.doc (1786368, 2007-01-29)
开发板实验例程\labdocs\03_global_time_const_lab_9.doc (2468864, 2007-01-31)
开发板实验例程\labdocs\04_Synthesis_lab_XST_9.doc (1099264, 2007-02-07)
开发板实验例程\labdocs\05_coregen_lab_9.doc (1645056, 2007-01-30)
开发板实验例程\labdocs\06_chipscope_lab_9.doc (3339264, 2007-01-31)
开发板实验例程\labs\verilog\lab2\arwz_pace.dhp (59029, 2005-04-27)
开发板实验例程\labs\verilog\lab2\arwz_pace.ise (312583, 2007-01-29)
开发板实验例程\labs\verilog\lab2\arwz_pace.ise.old (5266, 2006-01-13)
开发板实验例程\labs\verilog\lab2\arwz_pace.ise_ISE_Backup (312591, 2007-01-29)
开发板实验例程\labs\verilog\lab2\arwz_pace_ise7_bak.zip (30859, 2006-01-13)
开发板实验例程\labs\verilog\lab2\arwz_pace_ise9migration.zip (325491, 2007-01-29)
开发板实验例程\labs\verilog\lab2\bbfifo_16x8.v (13047, 2005-01-12)
开发板实验例程\labs\verilog\lab2\kcpsm3.v (95133, 2004-08-23)
开发板实验例程\labs\verilog\lab2\kcuart_rx.v (17999, 2005-01-12)
开发板实验例程\labs\verilog\lab2\kcuart_tx.v (12673, 2004-11-02)
开发板实验例程\labs\verilog\lab2\Project.dhp (1473, 2005-04-26)
开发板实验例程\labs\verilog\lab2\transcript (492, 2006-05-16)
开发板实验例程\labs\verilog\lab2\uart_clock.v (10154, 2006-06-08)
开发板实验例程\labs\verilog\lab2\uart_clock_summary.html (2397, 2007-01-29)
开发板实验例程\labs\verilog\lab2\uart_rx.v (4426, 2004-09-07)
开发板实验例程\labs\verilog\lab2\uart_rx_summary.html (2059, 2006-01-13)
开发板实验例程\labs\verilog\lab2\uart_tx.v (4413, 2004-09-07)
开发板实验例程\labs\verilog\lab2\UCLOCK.V (23267, 2006-05-22)
开发板实验例程\labs\verilog\lab2\__ISE_repository_arwz_pace.ise_.lock (198, 2007-01-29)
开发板实验例程\labs\verilog\lab3\Assembler\assemble.bat (27, 2005-02-02)
开发板实验例程\labs\verilog\lab3\Assembler\CONSTANT.TXT (2050, 2006-05-22)
开发板实验例程\labs\verilog\lab3\Assembler\KCPSM3.EXE (89320, 2004-09-23)
开发板实验例程\labs\verilog\lab3\Assembler\LABELS.TXT (95, 2006-05-22)
开发板实验例程\labs\verilog\lab3\Assembler\PASS1.DAT (17145, 2006-05-22)
开发板实验例程\labs\verilog\lab3\Assembler\PASS2.DAT (17145, 2006-05-22)
开发板实验例程\labs\verilog\lab3\Assembler\PASS3.DAT (19899, 2006-05-22)
开发板实验例程\labs\verilog\lab3\Assembler\PASS4.DAT (25895, 2006-05-22)
开发板实验例程\labs\verilog\lab3\Assembler\PASS5.DAT (36434, 2006-05-22)
开发板实验例程\labs\verilog\lab3\Assembler\PROGRAM.COE (8088, 2006-05-22)
开发板实验例程\labs\verilog\lab3\Assembler\PROGRAM.DEC (5125, 2006-05-22)
开发板实验例程\labs\verilog\lab3\Assembler\PROGRAM.FMT (9363, 2006-05-22)
开发板实验例程\labs\verilog\lab3\Assembler\PROGRAM.HEX (7168, 2006-05-22)
开发板实验例程\labs\verilog\lab3\Assembler\PROGRAM.LOG (11605, 2006-05-22)
开发板实验例程\labs\verilog\lab3\Assembler\PROGRAM.M (3734, 2006-05-22)
... ...

The following files were generated for 'program' in directory C:\XUP\Markets\PLDs\Workshops\courses\v82_fpga_flow\sp3e\labs\vhdl\lab6\chipscope\: program.asy: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core. program.mif: Memory Initialization File which is automatically generated by the CORE Generator System for some modules when a simulation flow is specified. A MIF data file is used to support HDL functional simulation of modules which use arrays of values. program.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA. program.sym: Please see the core data sheet. program.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. program.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design. program.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core. program.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design. program.xco: CORE Generator input file containing the parameters used to regenerate a core. program_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator. program_readme.txt: Text file indicating the files generated and how they are used. Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.

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