Verilog_UDP

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:123KB
下载次数:139
上传日期:2009-10-28 19:12:49
上 传 者longye199035
说明:  辛辛苦苦找到的UDP的资料,在verilog中UDP指的是用户定义的原语。比如说大家有时候会见到“primitive...table...endtable...endendprimitive”这样的代码段,在书上只能找到大概的解释。到网上查的话又老是跟TCP/IP的UDP冲突。所以特地搜集到了这个东西,希望能帮助大家解决“用户原语”相关的问题。
(UDP hard to find the information in verilog in the UDP refers to the user-defined primitives. For example, we sometimes see the " primitive ... table ... endtable ... endendprimitive" This code segment can only be found in the book about interpretation. The online search, then they are always with the TCP/IP, UDP conflict. So, specifically to collect this stuff, hoping to help people solve the " user of the original language" related issues.)

文件列表:
Verilog UDP.pdf (140372, 2009-10-22)

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