2

所属分类:VHDL/FPGA/Verilog
开发工具:WORD
文件大小:165KB
下载次数:7
上传日期:2009-11-01 17:17:19
上 传 者yu19870709
说明:  no intro
(Use maxplus2 completed one complete with hours, minutes, seconds, show 24h time functions 2, can complete the whole point timekeeping function, require that when the digital clock minutes, and seconds counter when the count to 59min52s, driver audio circuit, four high and one low, soon as the end of the last loud, the whole point of time to 3 to complete the " time" and " sub" when the school is also able to clear the seconds counter.)

文件列表:
报时式数字钟.doc (250880, 2009-11-01)

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