s_UIC_v3.03.tar

所属分类:VHDL/FPGA/Verilog
开发工具:VHDL
文件大小:2578KB
下载次数:11
上传日期:2009-11-06 11:26:19
上 传 者Franz
说明:  (IBM) Interrupter Controller for PowePC405 (verilog)

文件列表:
s_UIC_v3.03 (0, 2004-10-29)
s_UIC_v3.03\synthesis (0, 2004-10-29)
s_UIC_v3.03\synthesis\UIC.con.tcl (6655, 2004-10-29)
s_UIC_v3.03\synthesis\UIC.synopsys.tcl (10545, 2004-10-29)
s_UIC_v3.03\synthesis\.synopsys_dc.setup (865, 2004-10-29)
s_UIC_v3.03\synthesis\scan (0, 2004-10-29)
s_UIC_v3.03\synthesis\scan\UIC.con.tcl (6655, 2004-10-29)
s_UIC_v3.03\synthesis\scan\UIC.synopsys.tcl (17016, 2004-10-29)
s_UIC_v3.03\synthesis\scan\UIC.scan.tcl (12202, 2004-10-29)
s_UIC_v3.03\synthesis\scan\UIC.stil (21144, 2004-10-29)
s_UIC_v3.03\synthesis\scan\command.log (162122, 2004-10-29)
s_UIC_v3.03\synthesis\scan\UIC.db.justcompiled (224912, 2004-10-29)
s_UIC_v3.03\synthesis\scan\UIC.db.withscan (227360, 2004-10-29)
s_UIC_v3.03\synthesis\scan\design.log (1710, 2004-10-29)
s_UIC_v3.03\synthesis\scan\UIC.scanable.db (374816, 2004-10-29)
s_UIC_v3.03\synthesis\scan\Reference.log (9746, 2004-10-29)
s_UIC_v3.03\synthesis\scan\REPORT.log (1507295, 2004-10-29)
s_UIC_v3.03\synthesis\scan\UIC.slog (228975, 2004-10-29)
s_UIC_v3.03\synthesis\scan\UIC.mapped.v (249653, 2004-10-29)
s_UIC_v3.03\synthesis\scan\UIC.mapped.db (237728, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work (0, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\reg_gatedC1_ungatedC2-verilog.pvl (2491, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\REG_GATEDC1_UNGATEDC2.mr (23, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\reg_ungatedC1_gatedC2-verilog.pvl (2519, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\REG_UNGATEDC1_GATEDC2.mr (23, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\reg_ungatedC1_ungatedC2-verilog.pvl (2142, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\REG_UNGATEDC1_UNGATEDC2.mr (23, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\reg_ungatedC1_ungatedC2_enable-verilog.pvl (2429, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\REG_UNGATEDC1_UNGATEDC2_ENABLE.mr (23, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\reg_dff_busclocks-verilog.pvl (13550, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\REG_DFF_BUSCLOCKS.mr (23, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\rcvr-verilog.pvl (7157, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\RCVR.mr (23, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\uic_mac-verilog.pvl (25726, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\UIC_MAC.mr (23, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\UIC-verilog.pvl (4019, 2004-10-29)
s_UIC_v3.03\synthesis\scan\work\UIC.mr (23, 2004-10-29)
s_UIC_v3.03\primetime (0, 2004-10-29)
s_UIC_v3.03\primetime\UIC.primetime.tcl (6906, 2004-10-29)
... ...

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