watchdog
所属分类：VHDL/FPGA/Verilog
开发工具：VHDL
文件大小：4KB
下载次数：110
上传日期：2009-11-09 11:39:01
上 传 者：
佛少
说明： 看门狗定时器Verilog源码；用于MCU的辅助模块，定时特定的时间来做硬件复位，是用于避免固件跑死的一个机制。
(Watchdog verilog source.)
文件列表:
watchdog\CVS\Root (14, 2005-07-03)
watchdog\CVS\Repository (9, 2005-07-03)
watchdog\CVS\Entries (10, 2005-07-03)
watchdog\rtl\CVS\Root (14, 2005-07-03)
watchdog\rtl\CVS\Repository (13, 2005-07-03)
watchdog\rtl\CVS\Entries (14, 2005-07-03)
watchdog\rtl\verilog\CVS\Root (14, 2005-07-03)
watchdog\rtl\verilog\CVS\Repository (21, 2005-07-03)
watchdog\rtl\verilog\CVS\Entries (152, 2005-07-03)
watchdog\rtl\verilog\timescale.v (2351, 2002-10-14)
watchdog\rtl\verilog\watchdog.v (4509, 2002-10-14)
watchdog\rtl\verilog\watchdog_defines.v (2443, 2002-10-14)
watchdog\rtl\verilog\CVS (0, 2006-05-05)
watchdog\rtl\CVS (0, 2006-05-05)
watchdog\rtl\verilog (0, 2006-05-05)
watchdog\CVS (0, 2006-05-05)
watchdog\rtl (0, 2006-05-05)
watchdog (0, 2006-05-05)
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